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Message-ID: <Y9PvKurcZLva8Vws@axis.com>
Date: Fri, 27 Jan 2023 16:35:06 +0100
From: Vincent Whitchurch <vincent.whitchurch@...s.com>
To: Herbert Xu <herbert@...dor.apana.org.au>
CC: "davem@...emloft.net" <davem@...emloft.net>,
Jesper Nilsson <Jesper.Nilsson@...s.com>,
Lars Persson <Lars.Persson@...s.com>, kernel <kernel@...s.com>,
"linux-crypto@...r.kernel.org" <linux-crypto@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Christoph Hellwig <hch@....de>
Subject: Re: [PATCH 01/12] crypto: axis - do not DMA to ahash_request.result
On Fri, Jan 20, 2023 at 10:09:18AM +0100, Herbert Xu wrote:
> On Tue, Jan 10, 2023 at 02:50:31PM +0100, Vincent Whitchurch wrote:
> >
> > @@ -2216,6 +2220,14 @@ static void artpec6_crypto_complete_aead(struct crypto_async_request *req)
> >
> > static void artpec6_crypto_complete_hash(struct crypto_async_request *req)
> > {
> > + struct ahash_request *areq = container_of(req, struct ahash_request, base);
> > + struct artpec6_hash_request_context *ctx = ahash_request_ctx(areq);
> > + struct crypto_ahash *ahash = crypto_ahash_reqtfm(areq);
> > + size_t digestsize = crypto_ahash_digestsize(ahash);
> > +
> > + if (ctx->hash_flags & HASH_FLAG_FINALIZED)
> > + memcpy(areq->result, ctx->digeststate, digestsize);
> > +
>
> I was just looking through the driver and digeststate does not
> appear to be aligned to the DMA cacheline, should it be?
Yes, you're right, thanks, that buffer and a few others are missing
alignment annotations. I'll add a patch to fix that when I respin the
series.
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