| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <20230127164040.1047583-4-gatien.chevallier@foss.st.com>
Date: Fri, 27 Jan 2023 17:40:37 +0100
From: Gatien Chevallier <gatien.chevallier@...s.st.com>
To: <Oleksii_Moisieiev@...m.com>, <gregkh@...uxfoundation.org>,
<herbert@...dor.apana.org.au>, <davem@...emloft.net>,
<robh+dt@...nel.org>, <krzysztof.kozlowski+dt@...aro.org>,
<alexandre.torgue@...s.st.com>, <vkoul@...nel.org>,
<jic23@...nel.org>, <olivier.moysan@...s.st.com>,
<arnaud.pouliquen@...s.st.com>, <mchehab@...nel.org>,
<fabrice.gasnier@...s.st.com>, <ulf.hansson@...aro.org>,
<edumazet@...gle.com>, <kuba@...nel.org>, <pabeni@...hat.com>
CC: <linux-crypto@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-stm32@...md-mailman.stormreply.com>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, <dmaengine@...r.kernel.org>,
<linux-i2c@...r.kernel.org>, <linux-iio@...r.kernel.org>,
<alsa-devel@...a-project.org>, <linux-media@...r.kernel.org>,
<linux-mmc@...r.kernel.org>, <netdev@...r.kernel.org>,
<linux-phy@...ts.infradead.org>, <linux-serial@...r.kernel.org>,
<linux-spi@...r.kernel.org>, <linux-usb@...r.kernel.org>,
Gatien Chevallier <gatien.chevallier@...s.st.com>,
Loic PALLARDY <loic.pallardy@...com>
Subject: [PATCH v3 3/6] dt-bindings: bus: add STM32 System Bus
Document STM32 System Bus. This bus is intended to control firewall
access for the peripherals connected to it.
Signed-off-by: Gatien Chevallier <gatien.chevallier@...s.st.com>
Signed-off-by: Loic PALLARDY <loic.pallardy@...com>
---
Changes in V2:
- Corrected errors highlighted by Rob's robot
- Re-ordered Signed-off-by tags
Changes in V3:
- Correct #feature-domain-cells
- Declare 1 as minimum number of arguments for feature-domains property
in bus subnodes and 3 as maximum.
- Change example to be a real usecase.
.../devicetree/bindings/bus/st,sys-bus.yaml | 127 ++++++++++++++++++
1 file changed, 127 insertions(+)
create mode 100644 Documentation/devicetree/bindings/bus/st,sys-bus.yaml
diff --git a/Documentation/devicetree/bindings/bus/st,sys-bus.yaml b/Documentation/devicetree/bindings/bus/st,sys-bus.yaml
new file mode 100644
index 000000000000..c1510784b79b
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/st,sys-bus.yaml
@@ -0,0 +1,127 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bus/st,sys-bus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STM32 System Bus
+
+description: |
+ The STM32 System Bus is an internal bus to which some internal peripherals
+ are connected. STM32 System Bus integrates a firewall controlling access to each
+ device. This bus prevents non-accessible devices to be probed.
+
+ To see which peripherals are securable, please check the SoC reference manual.
+
+maintainers:
+ - Gatien Chevallier <gatien.chevallier@...s.st.com>
+
+allOf:
+ - $ref: /schemas/feature-controllers/feature-domain-controller.yaml#
+
+properties:
+ compatible:
+ enum:
+ - st,stm32mp13-sys-bus
+ - st,stm32mp15-sys-bus
+
+ reg:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ "#feature-domain-cells":
+ const: 1
+
+ ranges: true
+
+ feature-domain-controller: true
+
+patternProperties:
+ "^.*@[0-9a-f]+$":
+ description: Devices attached to system bus
+ type: object
+ properties:
+ feature-domains:
+ $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+ minItems: 1
+ maxItems: 3
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+ - feature-domain-controller
+ - "#feature-domain-cells"
+ - ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ // In this example, the rng1 device refers to etzpc as its domain controller.
+ // Same goes for fmc.
+ // Access rights are verified before creating devices.
+
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/stm32mp1-clks.h>
+ #include <dt-bindings/reset/stm32mp1-resets.h>
+
+ etzpc: bus@...07000 {
+ compatible = "st,stm32mp15-sys-bus";
+ reg = <0x5c007000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ feature-domain-controller;
+ #feature-domain-cells = <1>;
+
+ rng1: rng@...03000 {
+ compatible = "st,stm32-rng";
+ reg = <0x54003000 0x400>;
+ clocks = <&rcc RNG1_K>;
+ resets = <&rcc RNG1_R>;
+ feature-domains = <&etzpc 7>;
+ status = "disabled";
+ };
+
+ fmc: memory-controller@...02000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "st,stm32mp1-fmc2-ebi";
+ reg = <0x58002000 0x1000>;
+ clocks = <&rcc FMC_K>;
+ resets = <&rcc FMC_R>;
+ feature-domains = <&etzpc 91>;
+ status = "disabled";
+
+ ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
+ <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
+ <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
+ <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
+ <4 0 0x80000000 0x10000000>; /* NAND */
+
+ nand-controller@4,0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32mp1-fmc2-nfc";
+ reg = <4 0x00000000 0x1000>,
+ <4 0x08010000 0x1000>,
+ <4 0x08020000 0x1000>,
+ <4 0x01000000 0x1000>,
+ <4 0x09010000 0x1000>,
+ <4 0x09020000 0x1000>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
+ <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
+ <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
+ dma-names = "tx", "rx", "ecc";
+ status = "disabled";
+ };
+ };
+ };
--
2.35.3
Powered by blists - more mailing lists