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Message-Id: <20230127035306.1819561-1-guoren@kernel.org>
Date: Thu, 26 Jan 2023 22:53:06 -0500
From: guoren@...nel.org
To: arnd@...db.de, palmer@...osinc.com, conor.dooley@...rochip.com,
apatel@...tanamicro.com, atishp@...shpatra.org,
mark.rutland@....com, bjorn@...nel.org, guoren@...nel.org,
tongtiangen@...wei.com, ajones@...tanamicro.com, andrew@...ive.com
Cc: linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
Guo Ren <guoren@...ux.alibaba.com>
Subject: [PATCH V2] riscv: Fixup race condition on PG_dcache_clean in flush_icache_pte
From: Guo Ren <guoren@...ux.alibaba.com>
In commit 588a513d3425 ("arm64: Fix race condition on PG_dcache_clean
in __sync_icache_dcache()"), we found RISC-V has the same issue as the
previous arm64. The previous implementation didn't guarantee the correct
sequence of operations, which means flush_icache_all() hasn't been
called when the PG_dcache_clean was set. That would cause a risk of page
synchronization.
Fixes: 08f051eda33b ("RISC-V: Flush I$ when making a dirty page executable")
Signed-off-by: Guo Ren <guoren@...ux.alibaba.com>
Signed-off-by: Guo Ren <guoren@...nel.org>
---
Changelog:
V2:
- Optimize commit log
- Rebase on riscv for-next (20230127)
V1:
https://lore.kernel.org/linux-riscv/20221023133205.3493564-2-guoren@kernel.org/
---
arch/riscv/mm/cacheflush.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c
index 3cc07ed45aeb..fcd6145fbead 100644
--- a/arch/riscv/mm/cacheflush.c
+++ b/arch/riscv/mm/cacheflush.c
@@ -90,8 +90,10 @@ void flush_icache_pte(pte_t pte)
if (PageHuge(page))
page = compound_head(page);
- if (!test_and_set_bit(PG_dcache_clean, &page->flags))
+ if (!test_bit(PG_dcache_clean, &page->flags)) {
flush_icache_all();
+ set_bit(PG_dcache_clean, &page->flags);
+ }
}
#endif /* CONFIG_MMU */
--
2.36.1
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