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Message-ID: <Y9RV0cOMld20EFBI@spud>
Date: Fri, 27 Jan 2023 22:53:05 +0000
From: Conor Dooley <conor@...nel.org>
To: Atish Patra <atishp@...osinc.com>
Cc: linux-kernel@...r.kernel.org,
Andrew Jones <ajones@...tanamicro.com>,
Anup Patel <anup@...infault.org>,
Atish Patra <atishp@...shpatra.org>,
Guo Ren <guoren@...nel.org>, Heiko Stuebner <heiko@...ech.de>,
kvm-riscv@...ts.infradead.org, kvm@...r.kernel.org,
linux-riscv@...ts.infradead.org,
Mark Rutland <mark.rutland@....com>,
Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Sergey Matyukevich <sergey.matyukevich@...tacore.com>,
Will Deacon <will@...nel.org>
Subject: Re: [PATCH v3 03/14] RISC-V: Improve SBI PMU extension related
definitions
Yo Atish,
On Fri, Jan 27, 2023 at 10:25:47AM -0800, Atish Patra wrote:
> This patch fixes/improve few minor things in SBI PMU extension
> definition.
>
> 1. Align all the firmware event names.
> @@ -171,7 +171,7 @@ enum sbi_pmu_fw_generic_events_t {
> SBI_PMU_FW_IPI_RECVD = 7,
> - SBI_PMU_FW_FENCE_I_RECVD = 9,
> + SBI_PMU_FW_FENCE_I_RCVD = 9,
> SBI_PMU_FW_SFENCE_VMA_RCVD = 11,
Alignment looks incomplete to me! Looks like you went from 2 RECVD and
1 RCVD to 2 RCVD and 1 RECVD! FWIW, the spec uses RECEIVED for all of
these:
https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc#114-event-firmware-events-type-15
Thanks,
Conor.
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