Message-ID: <27472a10-7e14-de7e-6cec-b7a75647fcaa@quicinc.com>
Date:   Fri, 27 Jan 2023 12:32:34 +0530
From:   Mukesh Ojha <quic_mojha@...cinc.com>
To:     Randy Dunlap <rdunlap@...radead.org>,
        <linux-kernel@...r.kernel.org>
CC:     Catalin Marinas <catalin.marinas@....com>,
        Will Deacon <will@...nel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        Jonathan Corbet <corbet@....net>, <linux-doc@...r.kernel.org>
Subject: Re: [PATCH 01/35] Documentation: arm64: correct spelling



On 1/27/2023 12:09 PM, Randy Dunlap wrote:
> Correct spelling problems for Documentation/arm64/ as reported
> by codespell.
> 
> Signed-off-by: Randy Dunlap <rdunlap@...radead.org>
> Cc: Catalin Marinas <catalin.marinas@....com>
> Cc: Will Deacon <will@...nel.org>
> Cc: linux-arm-kernel@...ts.infradead.org
> Cc: Jonathan Corbet <corbet@....net>
> Cc: linux-doc@...r.kernel.org
> ---
>   Documentation/arm64/booting.rst    |    2 +-
>   Documentation/arm64/elf_hwcaps.rst |    2 +-
>   Documentation/arm64/sve.rst        |    4 ++--
>   3 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff -- a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst
> --- a/Documentation/arm64/booting.rst
> +++ b/Documentation/arm64/booting.rst
> @@ -223,7 +223,7 @@ Before jumping into the kernel, the foll
>     For systems with a GICv3 interrupt controller to be used in v3 mode:
>     - If EL3 is present:
>   
> -      - ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1.
> +      - ICC_SRE_EL3.Enable (bit 3) must be initialised to 0b1.
>         - ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
>         - ICC_CTLR_EL3.PMHE (bit 6) must be set to the same value across
>           all CPUs the kernel is executing on, and must stay constant
> diff -- a/Documentation/arm64/elf_hwcaps.rst b/Documentation/arm64/elf_hwcaps.rst
> --- a/Documentation/arm64/elf_hwcaps.rst
> +++ b/Documentation/arm64/elf_hwcaps.rst
> @@ -14,7 +14,7 @@ Some hardware or software features are o
>   implementations, and/or with certain kernel configurations, but have no
>   architected discovery mechanism available to userspace code at EL0. The
>   kernel exposes the presence of these features to userspace through a set
> -of flags called hwcaps, exposed in the auxilliary vector.
> +of flags called hwcaps, exposed in the auxiliary vector.
>   
>   Userspace software can test for features by acquiring the AT_HWCAP or
>   AT_HWCAP2 entry of the auxiliary vector, and testing whether the relevant
> diff -- a/Documentation/arm64/sve.rst b/Documentation/arm64/sve.rst
> --- a/Documentation/arm64/sve.rst
> +++ b/Documentation/arm64/sve.rst
> @@ -175,7 +175,7 @@ the SVE instruction set architecture.
>   When returning from a signal handler:
>   
>   * If there is no sve_context record in the signal frame, or if the record is
> -  present but contains no register data as desribed in the previous section,
> +  present but contains no register data as described in the previous section,
>     then the SVE registers/bits become non-live and take unspecified values.
>   
>   * If sve_context is present in the signal frame and contains full register
> @@ -223,7 +223,7 @@ prctl(PR_SVE_SET_VL, unsigned long arg)
>   	    Defer the requested vector length change until the next execve()
>   	    performed by this thread.
>   
> -	    The effect is equivalent to implicit exceution of the following
> +	    The effect is equivalent to implicit execution of the following
>   	    call immediately after the next execve() (if any) by the thread:
>   
>   		prctl(PR_SVE_SET_VL, arg & ~PR_SVE_SET_VL_ONEXEC)
> 

Reviewed-by: Mukesh Ojha <quic_mojha@...cinc.com>

-Mukesh

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