linux-kernel - Re: [PATCH V1 4/8] pinctrl: qcom: Add IPQ9574 pinctrl driver

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <3dc2b369-cdb5-f435-4c05-c67ec4ccbcea@quicinc.com>
Date:   Fri, 27 Jan 2023 14:46:54 +0530
From:   Devi Priya <quic_devipriy@...cinc.com>
To:     Konrad Dybcio <konrad.dybcio@...aro.org>, <agross@...nel.org>,
        <andersson@...nel.org>, <robh+dt@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>, <mturquette@...libre.com>,
        <sboyd@...nel.org>, <ulf.hansson@...aro.org>,
        <linus.walleij@...aro.org>, <catalin.marinas@....com>,
        <will@...nel.org>, <p.zabel@...gutronix.de>, <shawnguo@...nel.org>,
        <arnd@...db.de>, <marcel.ziswiler@...adex.com>,
        <dmitry.baryshkov@...aro.org>, <nfraprado@...labora.com>,
        <broonie@...nel.org>, <tdas@...eaurora.org>,
        <bhupesh.sharma@...aro.org>, <linux-arm-msm@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-clk@...r.kernel.org>, <linux-mmc@...r.kernel.org>,
        <linux-gpio@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>
CC:     <quic_srichara@...cinc.com>, <quic_gokulsri@...cinc.com>,
        <quic_sjaganat@...cinc.com>, <quic_kathirav@...cinc.com>,
        <quic_arajkuma@...cinc.com>, <quic_anusha@...cinc.com>,
        <quic_poovendh@...cinc.com>
Subject: Re: [PATCH V1 4/8] pinctrl: qcom: Add IPQ9574 pinctrl driver



On 1/26/2023 5:21 AM, Konrad Dybcio wrote:
> 
> 
> On 24.01.2023 15:15, devi priya wrote:
>> Add pinctrl definitions for the TLMM of IPQ9574
>>
>> Co-developed-by: Anusha Rao <quic_anusha@...cinc.com>
>> Signed-off-by: Anusha Rao <quic_anusha@...cinc.com>
>> Signed-off-by: devi priya <quic_devipriy@...cinc.com>
>> ---
> [...]
> 
>> +enum ipq9574_functions {
>> +	msm_mux_atest_char,
>> +	msm_mux_atest_char0,
>> +	msm_mux_atest_char1,
>> +	msm_mux_atest_char2,
>> +	msm_mux_atest_char3,
>> +	msm_mux_audio_pdm0,
>> +	msm_mux_audio_pdm1,
>> +	msm_mux_audio_pri,
>> +	msm_mux_audio_sec,
>> +	msm_mux_blsp0_spi,
>> +	msm_mux_blsp0_uart,
>> +	msm_mux_blsp1_i2c,
>> +	msm_mux_blsp1_spi,
>> +	msm_mux_blsp1_uart,
>> +	msm_mux_blsp2_i2c,
>> +	msm_mux_blsp2_spi,
>> +	msm_mux_blsp2_uart,
>> +	msm_mux_blsp3_i2c,
>> +	msm_mux_blsp3_spi,
>> +	msm_mux_blsp3_uart,
>> +	msm_mux_blsp4_i2c,
>> +	msm_mux_blsp4_spi,
>> +	msm_mux_blsp4_uart,
>> +	msm_mux_blsp5_i2c,
>> +	msm_mux_blsp5_uart,
>> +	msm_mux_cri_trng0,
>> +	msm_mux_cri_trng1,
>> +	msm_mux_cri_trng2,
>> +	msm_mux_cri_trng3,
>> +	msm_mux_cxc0,
>> +	msm_mux_cxc1,
>> +	msm_mux_dbg_out,
>> +	msm_mux_dwc_ddrphy,
>> +	msm_mux_gcc_plltest,
>> +	msm_mux_gcc_tlmm,
>> +	msm_mux_gpio,
> 
>> +	msm_mux_mac00,
>> +	msm_mux_mac01,
>> +	msm_mux_mac10,
>> +	msm_mux_mac11,
> msm_mux_mac?
Okay, will have msm_mux_mac enum instead of the above entries(00, 01, 
10, 11)
> 
>> +	msm_mux_mdc,
>> +	msm_mux_mdio,
>> +	msm_mux_pcie0_clk,
>> +	msm_mux_pcie0_wake,
>> +	msm_mux_pcie1_clk,
>> +	msm_mux_pcie1_wake,
>> +	msm_mux_pcie2_clk,
>> +	msm_mux_pcie2_wake,
>> +	msm_mux_pcie3_clk,
>> +	msm_mux_pcie3_wake,
>> +	msm_mux_prng_rosc0,
>> +	msm_mux_prng_rosc1,
>> +	msm_mux_prng_rosc2,
>> +	msm_mux_prng_rosc3,
> 
>> +	msm_mux_pta1_0,
>> +	msm_mux_pta1_1,
>> +	msm_mux_pta1_2,
>> +	msm_mux_pta20,
>> +	msm_mux_pta21,
> msm_mux_pta?
Okay
> 
>> +	msm_mux_pwm00,
>> +	msm_mux_pwm01,
>> +	msm_mux_pwm02,
>> +	msm_mux_pwm03,
>> +	msm_mux_pwm04,
>> +	msm_mux_pwm10,
>> +	msm_mux_pwm11,
>> +	msm_mux_pwm12,
>> +	msm_mux_pwm13,
>> +	msm_mux_pwm14,
>> +	msm_mux_pwm20,
>> +	msm_mux_pwm21,
>> +	msm_mux_pwm22,
>> +	msm_mux_pwm23,
>> +	msm_mux_pwm24,
>> +	msm_mux_pwm30,
>> +	msm_mux_pwm31,
>> +	msm_mux_pwm32,
>> +	msm_mux_pwm33,
> msm_mux_pwm?
Okay
> 
> [...]
> 
>> +
>> +static const int ipq9574_reserved_gpios[] = {
>> +	59, -1
>> +};
> We know it's necessary and it's good that you take care
> of it, but it would be even nicer if you left a comment
> explaining why the rx0/pwm23/qdss_tracedata_a gpio can
> not be accessed and what it's used for.
> 
Sure, will add comments in V3
Reserving the GPIO as it is used for controlling the QFPROM LDO 
regulator by the security component
> Konrad
>> +
>> +static const struct msm_pinctrl_soc_data ipq9574_pinctrl = {
>> +	.pins = ipq9574_pins,
>> +	.npins = ARRAY_SIZE(ipq9574_pins),
>> +	.functions = ipq9574_functions,
>> +	.nfunctions = ARRAY_SIZE(ipq9574_functions),
>> +	.groups = ipq9574_groups,
>> +	.ngroups = ARRAY_SIZE(ipq9574_groups),
>> +	.reserved_gpios = ipq9574_reserved_gpios,
>> +	.ngpios = 65,
>> +};
>> +
>> +static int ipq9574_pinctrl_probe(struct platform_device *pdev)
>> +{
>> +	return msm_pinctrl_probe(pdev, &ipq9574_pinctrl);
>> +}
>> +
>> +static const struct of_device_id ipq9574_pinctrl_of_match[] = {
>> +	{ .compatible = "qcom,ipq9574-tlmm", },
>> +	{ },
>> +};
>> +
>> +static struct platform_driver ipq9574_pinctrl_driver = {
>> +	.driver = {
>> +		.name = "ipq9574-tlmm",
>> +		.of_match_table = ipq9574_pinctrl_of_match,
>> +	},
>> +	.probe = ipq9574_pinctrl_probe,
>> +	.remove = msm_pinctrl_remove,
>> +};
>> +
>> +static int __init ipq9574_pinctrl_init(void)
>> +{
>> +	return platform_driver_register(&ipq9574_pinctrl_driver);
>> +}
>> +arch_initcall(ipq9574_pinctrl_init);
>> +
>> +static void __exit ipq9574_pinctrl_exit(void)
>> +{
>> +	platform_driver_unregister(&ipq9574_pinctrl_driver);
>> +}
>> +module_exit(ipq9574_pinctrl_exit);
>> +
>> +MODULE_DESCRIPTION("QTI IPQ9574 TLMM driver");
>> +MODULE_LICENSE("GPL");
>> +MODULE_DEVICE_TABLE(of, ipq9574_pinctrl_of_match);
Best Regards,
Devi Priya