| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <dd51102c-79a8-1705-85f2-b82363cbe34a@starfivetech.com>
Date: Mon, 30 Jan 2023 14:17:16 +0800
From: Xingyu Wu <xingyu.wu@...rfivetech.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
<linux-riscv@...ts.infradead.org>, <devicetree@...r.kernel.org>,
"Michael Turquette" <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
Emil Renner Berthing <kernel@...il.dk>
CC: Rob Herring <robh+dt@...nel.org>, Conor Dooley <conor@...nel.org>,
"Paul Walmsley" <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Hal Feng <hal.feng@...rfivetech.com>,
<linux-kernel@...r.kernel.org>, <linux-clk@...r.kernel.org>
Subject: Re: [PATCH v1 01/11] dt-bindings: clock: Add StarFive JH7110
System-Top-Group clock and reset generator
On 2023/1/20 16:11, Krzysztof Kozlowski wrote:
> On 20/01/2023 03:44, Xingyu Wu wrote:
>> Add bindings for the System-Top-Group clock and reset generator (STGCRG)
>> on the JH7110 RISC-V SoC by StarFive Ltd.
>>
>> Signed-off-by: Xingyu Wu <xingyu.wu@...rfivetech.com>
>> ---
>> .../clock/starfive,jh7110-stgcrg.yaml | 82 +++++++++++++++++++
>> MAINTAINERS | 2 +
>> .../dt-bindings/clock/starfive,jh7110-crg.h | 34 ++++++++
>> .../dt-bindings/reset/starfive,jh7110-crg.h | 28 +++++++
>> 4 files changed, 146 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml
>> new file mode 100644
>> index 000000000000..b64ccd84200a
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml
>> @@ -0,0 +1,82 @@
>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/starfive,jh7110-stgcrg.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: StarFive JH7110 System-Top-Group Clock and Reset Generator
>> +
>> +maintainers:
>> + - Xingyu Wu <xingyu.wu@...rfivetech.com>
>> +
>> +properties:
>> + compatible:
>> + const: starfive,jh7110-stgcrg
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + clocks:
>> + items:
>> + - description: Main Oscillator (24 MHz)
>> + - description: HIFI4 core
>> + - description: STG AXI/AHB
>> + - description: USB (125 MHz)
>> + - description: CPU Bus
>> + - description: HIFI4 Axi
>> + - description: NOC STG Bus
>> + - description: APB Bus
>> +
>> + clock-names:
>> + items:
>> + - const: osc
>> + - const: hifi4_core
>> + - const: stg_axiahb
>> + - const: usb_125m
>> + - const: cpu_bus
>> + - const: hifi4_axi
>> + - const: nocstg_bus
>> + - const: apb_bus
>> +
>> + '#clock-cells':
>> + const: 1
>> + description:
>> + See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
>> +
>> + '#reset-cells':
>> + const: 1
>> + description:
>> + See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - clocks
>> + - clock-names
>> + - '#clock-cells'
>> + - '#reset-cells'
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/starfive,jh7110-crg.h>
>> +
>> + stgcrg: clock-controller@...30000 {
>> + compatible = "starfive,jh7110-stgcrg";
>> + reg = <0x10230000 0x10000>;
>> + clocks = <&osc>,
>> + <&syscrg JH7110_SYSCLK_HIFI4_CORE>,
>> + <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
>> + <&syscrg JH7110_SYSCLK_USB_125M>,
>> + <&syscrg JH7110_SYSCLK_CPU_BUS>,
>> + <&syscrg JH7110_SYSCLK_HIFI4_AXI>,
>> + <&syscrg JH7110_SYSCLK_NOCSTG_BUS>,
>> + <&syscrg JH7110_SYSCLK_APB_BUS>;
>> + clock-names = "osc", "hifi4_core",
>> + "stg_axiahb", "usb_125m",
>> + "cpu_bus", "hifi4_axi",
>> + "nocstg_bus", "apb_bus";
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + };
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 84fd7054cb6e..20243eb5470c 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -19635,6 +19635,7 @@ F: arch/riscv/boot/dts/starfive/
>> STARFIVE JH71X0 CLOCK DRIVERS
>> M: Emil Renner Berthing <kernel@...il.dk>
>> M: Hal Feng <hal.feng@...rfivetech.com>
>> +M: Xingyu Wu <xingyu.wu@...rfivetech.com>
>
> Not related, drop from this patch.
This patch is about JH7110 STG/VOUT/ISP clock driver which belong to
JH71X0 clock driver.
>
>> S: Maintained
>> F: Documentation/devicetree/bindings/clock/starfive,jh71*.yaml
>> F: drivers/clk/starfive/clk-starfive-jh71*
>> @@ -19654,6 +19655,7 @@ F: include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h
>> STARFIVE JH71X0 RESET CONTROLLER DRIVERS
>> M: Emil Renner Berthing <kernel@...il.dk>
>> M: Hal Feng <hal.feng@...rfivetech.com>
>> +M: Xingyu Wu <xingyu.wu@...rfivetech.com>
>
> Not related.
>
>> S: Maintained
>> F: Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
>> F: drivers/reset/starfive/reset-starfive-jh71*
>> diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h
>> index 5e4f21ca0642..5ac8a4d90a7a 100644
>> --- a/include/dt-bindings/clock/starfive,jh7110-crg.h
>> +++ b/include/dt-bindings/clock/starfive,jh7110-crg.h
>> @@ -1,6 +1,7 @@
>> /* SPDX-License-Identifier: GPL-2.0 OR MIT */
>> /*
>> * Copyright 2022 Emil Renner Berthing <kernel@...il.dk>
>> + * Copyright 2022 StarFive Technology Co., Ltd.
>> */
>>
>> #ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
>> @@ -222,4 +223,37 @@
>>
>> #define JH7110_AONCLK_END 14
>>
>> +/* STGCRG clocks */
>> +#define JH7110_STGCLK_HIFI4_CLK_CORE 0
>> +#define JH7110_STGCLK_USB0_APB 1
>> +#define JH7110_STGCLK_USB0_UTMI_APB 2
>> +#define JH7110_STGCLK_USB0_AXI 3
>> +#define JH7110_STGCLK_USB0_LPM 4
>> +#define JH7110_STGCLK_USB0_STB 5
>> +#define JH7110_STGCLK_USB0_APP_125 6
>> +#define JH7110_STGCLK_USB0_REFCLK 7
>> +#define JH7110_STGCLK_PCIE0_AXI_MST0 8
>> +#define JH7110_STGCLK_PCIE0_APB 9
>> +#define JH7110_STGCLK_PCIE0_TL 10
>> +#define JH7110_STGCLK_PCIE1_AXI_MST0 11
>> +#define JH7110_STGCLK_PCIE1_APB 12
>> +#define JH7110_STGCLK_PCIE1_TL 13
>> +#define JH7110_STGCLK_PCIE01_SLV_DEC_MAINCLK 14
>> +#define JH7110_STGCLK_SEC_HCLK 15
>> +#define JH7110_STGCLK_SEC_MISCAHB 16
>> +#define JH7110_STGCLK_GRP0_MAIN 17
>> +#define JH7110_STGCLK_GRP0_BUS 18
>> +#define JH7110_STGCLK_GRP0_STG 19
>> +#define JH7110_STGCLK_GRP1_MAIN 20
>> +#define JH7110_STGCLK_GRP1_BUS 21
>> +#define JH7110_STGCLK_GRP1_STG 22
>> +#define JH7110_STGCLK_GRP1_HIFI 23
>> +#define JH7110_STGCLK_E2_RTC 24
>> +#define JH7110_STGCLK_E2_CORE 25
>> +#define JH7110_STGCLK_E2_DBG 26
>> +#define JH7110_STGCLK_DMA1P_AXI 27
>> +#define JH7110_STGCLK_DMA1P_AHB 28
>> +
>> +#define JH7110_STGCLK_END 29
>> +
>> #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */
>> diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h
>> index d78e38690ceb..cb70a1759482 100644
>> --- a/include/dt-bindings/reset/starfive,jh7110-crg.h
>> +++ b/include/dt-bindings/reset/starfive,jh7110-crg.h
>> @@ -1,6 +1,7 @@
>> /* SPDX-License-Identifier: GPL-2.0 OR MIT */
>> /*
>> * Copyright (C) 2022 Emil Renner Berthing <kernel@...il.dk>
>> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
>> */
>>
>> #ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__
>> @@ -151,4 +152,31 @@
>>
>> #define JH7110_AONRST_END 8
>>
>> +/* STGCRG resets */
>> +#define JH7110_STGRST_SYSCON 0
>
> Drop weird indentation.
Will fix in next patch.
Best regards.
Xingyu Wu
Powered by blists - more mailing lists