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Message-ID: <20230130073522.ivv2izzayouhw6dm@orel>
Date: Mon, 30 Jan 2023 08:35:22 +0100
From: Andrew Jones <ajones@...tanamicro.com>
To: Liao Chang <liaochang1@...wei.com>
Cc: paul.walmsley@...ive.com, palmer@...belt.com,
aou@...s.berkeley.edu, heiko.stuebner@...ll.eu,
prabhakar.mahadev-lad.rj@...renesas.com,
conor.dooley@...rochip.com, jszhang@...nel.org,
vincent.chen@...ive.com, linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH] riscv: Add header include guards to insn.h
On Sun, Jan 29, 2023 at 05:42:42PM +0800, Liao Chang wrote:
> Add header include guards to insn.h to prevent repeating declaration of
> any identifiers in insn.h.
>
> Fixes: edde5584c7ab ("riscv: Add SW single-step support for KDB")
> Signed-off-by: Liao Chang <liaochang1@...wei.com>
> ---
> arch/riscv/include/asm/insn.h | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h
> index 25ef9c0b19e7..22c7613bfda3 100644
> --- a/arch/riscv/include/asm/insn.h
> +++ b/arch/riscv/include/asm/insn.h
> @@ -3,6 +3,9 @@
> * Copyright (C) 2020 SiFive
> */
>
> +#ifndef _ASM_RISCV_INSN_H
> +#define _ASM_RISCV_INSN_H
> +
> #include <linux/bits.h>
>
> #define RV_INSN_FUNCT3_MASK GENMASK(14, 12)
> @@ -365,3 +368,4 @@ static inline void riscv_insn_insert_utype_itype_imm(u32 *utype_insn, u32 *itype
> *utype_insn |= (imm & RV_U_IMM_31_12_MASK) + ((imm & BIT(11)) << 1);
> *itype_insn |= ((imm & RV_I_IMM_11_0_MASK) << RV_I_IMM_11_0_OPOFF);
> }
> +#endif /* _ASM_RISCV_INSN_H */
> --
> 2.25.1
>
Reviewed-by: Andrew Jones <ajones@...tanamicro.com>
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