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Message-ID: <ce15c2be-e959-334a-2297-cfbb6bc2d62f@starfivetech.com>
Date: Mon, 30 Jan 2023 16:10:16 +0800
From: Xingyu Wu <xingyu.wu@...rfivetech.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
<linux-riscv@...ts.infradead.org>, <devicetree@...r.kernel.org>,
"Michael Turquette" <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
Emil Renner Berthing <kernel@...il.dk>
CC: Rob Herring <robh+dt@...nel.org>, Conor Dooley <conor@...nel.org>,
"Paul Walmsley" <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Hal Feng <hal.feng@...rfivetech.com>,
<linux-kernel@...r.kernel.org>, <linux-clk@...r.kernel.org>
Subject: Re: [PATCH v1 07/11] dt-bindings: clock: Add StarFive JH7110
Video-Output clock and reset generator
On 2023/1/20 16:13, Krzysztof Kozlowski wrote:
> On 20/01/2023 03:44, Xingyu Wu wrote:
>> Add bindings for the Video-Output clock and reset generator (VOUTCRG)
>> on the JH7110 RISC-V SoC by StarFive Ltd.
>>
>> Signed-off-by: Xingyu Wu <xingyu.wu@...rfivetech.com>
>> ---
>> .../clock/starfive,jh7110-voutcrg.yaml | 96 +++++++++++++++++++
>> .../dt-bindings/clock/starfive,jh7110-crg.h | 22 +++++
>> .../dt-bindings/reset/starfive,jh7110-crg.h | 16 ++++
>> 3 files changed, 134 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml
>> new file mode 100644
>> index 000000000000..a6a43d86a392
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml
>> @@ -0,0 +1,96 @@
>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/starfive,jh7110-voutcrg.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: StarFive JH7110 Video-Output Clock and Reset Generator
>> +
>> +maintainers:
>> + - Xingyu Wu <xingyu.wu@...rfivetech.com>
>> +
>> +properties:
>> + compatible:
>> + const: starfive,jh7110-voutcrg
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + clocks:
>> + items:
>> + - description: Vout Top core
>> + - description: Vout Top Ahb
>> + - description: Vout Top Axi
>> + - description: Vout Top HDMI MCLK
>> + - description: I2STX0 BCLK
>> + - description: external HDMI pixel
>> +
>> + clock-names:
>> + items:
>> + - const: vout_src
>> + - const: vout_top_ahb
>> + - const: vout_top_axi
>> + - const: vout_top_hdmitx0_mclk
>> + - const: i2stx0_bclk
>> + - const: hdmitx0_pixelclk
>> +
>> + resets:
>> + items:
>> + - description: Vout Top core
>> +
>> + reset-names:
>> + items:
>> + - const: vout_top_src
>> +
>> + '#clock-cells':
>> + const: 1
>> + description:
>> + See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
>> +
>> + '#reset-cells':
>> + const: 1
>> + description:
>> + See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
>> +
>> + power-domains:
>> + maxItems: 1
>> + description:
>> + Vout domain power
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - clocks
>> + - clock-names
>> + - resets
>> + - reset-names
>> + - '#clock-cells'
>> + - '#reset-cells'
>> + - power-domains
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/starfive,jh7110-crg.h>
>> + #include <dt-bindings/power/starfive,jh7110-pmu.h>
>> + #include <dt-bindings/reset/starfive,jh7110-crg.h>
>> +
>> + voutcrg: clock-controller@...C0000 {
>> + compatible = "starfive,jh7110-voutcrg";
>> + reg = <0x295C0000 0x10000>;
>> + clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>,
>> + <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>,
>> + <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>,
>> + <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>,
>> + <&syscrg JH7110_SYSCLK_I2STX0_BCLK>,
>> + <&hdmitx0_pixelclk>;
>> + clock-names = "vout_src", "vout_top_ahb",
>> + "vout_top_axi", "vout_top_hdmitx0_mclk",
>> + "i2stx0_bclk", "hdmitx0_pixelclk";
>> + resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>;
>> + reset-names = "vout_top_src";
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + power-domains = <&pwrc JH7110_PD_VOUT>;
>> + };
>> diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h
>> index 91ee589809c3..3ebece93cbd3 100644
>> --- a/include/dt-bindings/clock/starfive,jh7110-crg.h
>> +++ b/include/dt-bindings/clock/starfive,jh7110-crg.h
>> @@ -274,4 +274,26 @@
>>
>> #define JH7110_ISPCLK_END 14
>>
>> +/* VOUTCRG clocks */
>> +#define JH7110_VOUTCLK_APB 0
>> +#define JH7110_VOUTCLK_DC8200_PIX 1
>> +#define JH7110_VOUTCLK_DSI_SYS 2
>> +#define JH7110_VOUTCLK_TX_ESC 3
>> +#define JH7110_VOUTCLK_DC8200_AXI 4
>> +#define JH7110_VOUTCLK_DC8200_CORE 5
>> +#define JH7110_VOUTCLK_DC8200_AHB 6
>> +#define JH7110_VOUTCLK_DC8200_PIX0 7
>> +#define JH7110_VOUTCLK_DC8200_PIX1 8
>> +#define JH7110_VOUTCLK_DOM_VOUT_TOP_LCD 9
>> +#define JH7110_VOUTCLK_DSITX_APB 10
>> +#define JH7110_VOUTCLK_DSITX_SYS 11
>> +#define JH7110_VOUTCLK_DSITX_DPI 12
>> +#define JH7110_VOUTCLK_DSITX_TXESC 13
>> +#define JH7110_VOUTCLK_MIPITX_DPHY_TXESC 14
>> +#define JH7110_VOUTCLK_HDMI_TX_MCLK 15
>> +#define JH7110_VOUTCLK_HDMI_TX_BCLK 16
>> +#define JH7110_VOUTCLK_HDMI_TX_SYS 17
>> +
>> +#define JH7110_VOUTCLK_END 18
>> +
>> #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */
>> diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h
>> index 1b40df62cdac..f89589610cf5 100644
>> --- a/include/dt-bindings/reset/starfive,jh7110-crg.h
>> +++ b/include/dt-bindings/reset/starfive,jh7110-crg.h
>> @@ -195,4 +195,20 @@
>>
>> #define JH7110_ISPRST_END 12
>>
>> +/* VOUTCRG resets */
>> +#define JH7110_VOUTRST_DC8200_AXI 0
>> +#define JH7110_VOUTRST_DC8200_AHB 1
>
> Ditto
Will fix.
Best regards,
Xingyu Wu
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