linux-kernel - Re: [PATCH 5/8] PCI: rockchip: Added dtsi entry for PCIe endpoint controller

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Message-ID: <CAL_JsqJSZ7v-YSOyUu2zJ0Yu2pU+qm=hRtoyQpdmQdhs1tirDg@mail.gmail.com>
Date:   Mon, 30 Jan 2023 09:04:41 -0600
From:   Rob Herring <robh+dt@...nel.org>
To:     Rick Wertenbroek <rick.wertenbroek@...il.com>
Cc:     alberto.dassatti@...g-vd.ch, xxm@...k-chips.com,
        wenrui.li@...k-chips.com, rick.wertenbroek@...g-vd.ch,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Heiko Stuebner <heiko@...ech.de>,
        Shawn Lin <shawn.lin@...k-chips.com>,
        Lorenzo Pieralisi <lpieralisi@...nel.org>,
        Krzysztof Wilczyński <kw@...ux.com>,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        Jani Nikula <jani.nikula@...el.com>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Mikko Kovanen <mikko.kovanen@...amobile.com>,
        Rodrigo Vivi <rodrigo.vivi@...el.com>,
        devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-pci@...r.kernel.org
Subject: Re: [PATCH 5/8] PCI: rockchip: Added dtsi entry for PCIe endpoint controller

On Thu, Jan 26, 2023 at 7:52 AM Rick Wertenbroek
<rick.wertenbroek@...il.com> wrote:
>
> Added missing PCIe endpoint controller entry in the device tree. This
> entry is documented in :
> Documentation/devicetree/bindings/pci/rockchip-pcie-ep.txt
> The status is disabled by default, so it will not be loaded unless
> explicitly chosen to.
>
> Signed-off-by: Rick Wertenbroek <rick.wertenbroek@...il.com>
> ---
>  arch/arm64/boot/dts/rockchip/rk3399.dtsi | 25 ++++++++++++++++++++++++
>  1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> index 9d5b0e8c9..5f7251118 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> @@ -265,6 +265,31 @@ pcie0_intc: interrupt-controller {
>                 };
>         };
>
> +       pcie0_ep: pcie-ep@...00000 {
> +               compatible = "rockchip,rk3399-pcie-ep";
> +               #address-cells = <3>;
> +               #size-cells = <2>;

These are only needed when you have child nodes. Additionally, it
would not be a PCI bus which is the only case that has 3 address
cells.

There's a schema for this in linux-next now. Please test this change
with that. It should point out the above issue and maybe others.

> +               rockchip,max-outbound-regions = <32>;
> +               clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
> +                       <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
> +               clock-names = "aclk", "aclk-perf",
> +                               "hclk", "pm";
> +               max-functions = /bits/ 8 <8>;
> +               num-lanes = <4>;
> +               reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0xfa000000 0x0 0x2000000>;
> +               reg-names = "apb-base", "mem-base";
> +               resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
> +                       <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
> +                       <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
> +               reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
> +                               "pm", "pclk", "aclk";
> +               phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
> +               phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
> +               pinctrl-names = "default";
> +               pinctrl-0 = <&pcie_clkreqnb_cpm>;
> +               status = "disabled";
> +       };
> +
>         gmac: ethernet@...00000 {
>                 compatible = "rockchip,rk3399-gmac";
>                 reg = <0x0 0xfe300000 0x0 0x10000>;
> --
> 2.25.1
>