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Message-ID: <20230131173347.GA3602051@roeck-us.net>
Date: Tue, 31 Jan 2023 09:33:47 -0800
From: Guenter Roeck <linux@...ck-us.net>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Cc: Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Thomas Gleixner <tglx@...utronix.de>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Wim Van Sebroeck <wim@...ux-watchdog.org>,
Prakash Ranjan <saiprakash.ranjan@...eaurora.org>,
linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, linux-watchdog@...r.kernel.org
Subject: Re: [PATCH 06/12] dt-bindings: watchdog: qcom-wdt: merge MSM timer
On Mon, Dec 12, 2022 at 05:35:26PM +0100, Krzysztof Kozlowski wrote:
> Merge Qualcomm MSM timer bindings into watchdog, because the timer
> compatibles are already included here and the hardware is quite similar.
>
> While converting the MSM timer bindings, adjust clock-frequency
> property to take only one frequency, instead of two, because:
> 1. DT schema does not allow to frequencies,
> 2. The Linux timer driver reads only first frequency.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> Acked-by: Daniel Lezcano <daniel.lezcano@...aro.org>
Reviewed-by: Guenter Roeck <linux@...ck-us.net>
> ---
> .../bindings/timer/qcom,msm-timer.txt | 47 ------------------
> .../bindings/watchdog/qcom-wdt.yaml | 49 +++++++++++++++++++
> 2 files changed, 49 insertions(+), 47 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/timer/qcom,msm-timer.txt
>
> diff --git a/Documentation/devicetree/bindings/timer/qcom,msm-timer.txt b/Documentation/devicetree/bindings/timer/qcom,msm-timer.txt
> deleted file mode 100644
> index 5e10c345548f..000000000000
> --- a/Documentation/devicetree/bindings/timer/qcom,msm-timer.txt
> +++ /dev/null
> @@ -1,47 +0,0 @@
> -* MSM Timer
> -
> -Properties:
> -
> -- compatible : Should at least contain "qcom,msm-timer". More specific
> - properties specify which subsystem the timers are paired with.
> -
> - "qcom,kpss-timer" - krait subsystem
> - "qcom,scss-timer" - scorpion subsystem
> -
> -- interrupts : Interrupts for the debug timer, the first general purpose
> - timer, and optionally a second general purpose timer, and
> - optionally as well, 2 watchdog interrupts, in that order.
> -
> -- reg : Specifies the base address of the timer registers.
> -
> -- clocks: Reference to the parent clocks, one per output clock. The parents
> - must appear in the same order as the clock names.
> -
> -- clock-names: The name of the clocks as free-form strings. They should be in
> - the same order as the clocks.
> -
> -- clock-frequency : The frequency of the debug timer and the general purpose
> - timer(s) in Hz in that order.
> -
> -Optional:
> -
> -- cpu-offset : per-cpu offset used when the timer is accessed without the
> - CPU remapping facilities. The offset is
> - cpu-offset + (0x10000 * cpu-nr).
> -
> -Example:
> -
> - timer@...a000 {
> - compatible = "qcom,scss-timer", "qcom,msm-timer";
> - interrupts = <1 1 0x301>,
> - <1 2 0x301>,
> - <1 3 0x301>,
> - <1 4 0x301>,
> - <1 5 0x301>;
> - reg = <0x0200a000 0x100>;
> - clock-frequency = <19200000>,
> - <32768>;
> - clocks = <&sleep_clk>;
> - clock-names = "sleep";
> - cpu-offset = <0x40000>;
> - };
> diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml
> index b7fc57f4800e..697caf1937cc 100644
> --- a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml
> +++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml
> @@ -10,6 +10,9 @@ maintainers:
> - Sai Prakash Ranjan <saiprakash.ranjan@...eaurora.org>
>
> properties:
> + $nodename:
> + pattern: "^(watchdog|timer)@[0-9a-f]+$"
> +
> compatible:
> oneOf:
> - items:
> @@ -48,6 +51,20 @@ properties:
> clocks:
> maxItems: 1
>
> + clock-names:
> + items:
> + - const: sleep
> +
> + clock-frequency:
> + description:
> + The frequency of the general purpose timer in Hz in that order.
> +
> + cpu-offset:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + Per-CPU offset used when the timer is accessed without the CPU remapping
> + facilities. The offset is cpu-offset + (0x10000 * cpu-nr).
> +
> interrupts:
> minItems: 1
> maxItems: 5
> @@ -67,12 +84,27 @@ allOf:
> const: qcom,kpss-wdt
> then:
> properties:
> + clock-frequency: false
> + cpu-offset: false
> interrupts:
> minItems: 1
> items:
> - description: Bark
> - description: Bite
>
> + else:
> + properties:
> + interrupts:
> + minItems: 3
> + items:
> + - description: Debug
> + - description: First general purpose timer
> + - description: Second general purpose timer
> + - description: First watchdog
> + - description: Second watchdog
> + required:
> + - clock-frequency
> +
> unevaluatedProperties: false
>
> examples:
> @@ -86,3 +118,20 @@ examples:
> interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> timeout-sec = <10>;
> };
> +
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + watchdog@...a000 {
> + compatible = "qcom,kpss-wdt-ipq8064", "qcom,kpss-timer", "qcom,msm-timer";
> + interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
> + <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
> + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
> + <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
> + <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
> + reg = <0x0200a000 0x100>;
> + clock-frequency = <25000000>;
> + clocks = <&sleep_clk>;
> + clock-names = "sleep";
> + cpu-offset = <0x80000>;
> + };
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