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Message-ID: <AS8PR04MB86766A39B64D9C4B8E6787DF8CD09@AS8PR04MB8676.eurprd04.prod.outlook.com>
Date: Tue, 31 Jan 2023 07:53:14 +0000
From: Hongxing Zhu <hongxing.zhu@....com>
To: Rob Herring <robh@...nel.org>
CC: "krzysztof.kozlowski+dt@...aro.org"
<krzysztof.kozlowski+dt@...aro.org>,
"l.stach@...gutronix.de" <l.stach@...gutronix.de>,
"shawnguo@...nel.org" <shawnguo@...nel.org>,
"lorenzo.pieralisi@....com" <lorenzo.pieralisi@....com>,
Peng Fan <peng.fan@....com>, "marex@...x.de" <marex@...x.de>,
Marcel Ziswiler <marcel.ziswiler@...adex.com>,
"tharvey@...eworks.com" <tharvey@...eworks.com>,
Frank Li <frank.li@....com>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"kernel@...gutronix.de" <kernel@...gutronix.de>,
dl-linux-imx <linux-imx@....com>
Subject: RE: [PATCH v7 2/5] dt-bindings: imx6q-pcie: Add schema for i.MX8M
PCIe Endpoint modes
> -----Original Message-----
> From: Rob Herring <robh@...nel.org>
> Sent: 2023年1月31日 6:30
> To: Hongxing Zhu <hongxing.zhu@....com>
> Cc: krzysztof.kozlowski+dt@...aro.org; l.stach@...gutronix.de;
> shawnguo@...nel.org; lorenzo.pieralisi@....com; Peng Fan
> <peng.fan@....com>; marex@...x.de; Marcel Ziswiler
> <marcel.ziswiler@...adex.com>; tharvey@...eworks.com; Frank Li
> <frank.li@....com>; devicetree@...r.kernel.org;
> linux-arm-kernel@...ts.infradead.org; linux-kernel@...r.kernel.org;
> kernel@...gutronix.de; dl-linux-imx <linux-imx@....com>
> Subject: Re: [PATCH v7 2/5] dt-bindings: imx6q-pcie: Add schema for i.MX8M
> PCIe Endpoint modes
>
> On Mon, Jan 30, 2023 at 11:32:16AM +0800, Richard Zhu wrote:
> > Add support for i.MX8M PCIe Endpoint modes, and update the MAINTAINER
> > accordingly.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@....com>
> > ---
> > .../bindings/pci/fsl,imx6q-pcie-ep.yaml | 317
> ++++++++++++++++++
> > MAINTAINERS | 1 +
> > 2 files changed, 318 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
> > b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
> > new file mode 100644
> > index 000000000000..7c594ae53067
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
> > @@ -0,0 +1,317 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> > +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> >
> +cetree.org%2Fschemas%2Fpci%2Ffsl%2Cimx6q-pcie-ep.yaml%23&data=05
> %7C01
> >
> +%7Chongxing.zhu%40nxp.com%7C98e38ab75655406d3dea08db031176da%
> 7C686ea1
> >
> +d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C638107145768672999%7CU
> nknown%7CT
> >
> +WFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiL
> CJXVC
> >
> +I6Mn0%3D%7C3000%7C%7C%7C&sdata=nQJ9N2mnl3fAmwmyXsERqzsuDo
> %2FgzyDxpBD5
> > +c0LqizM%3D&reserved=0
> > +$schema:
> > +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> >
> +cetree.org%2Fmeta-schemas%2Fcore.yaml%23&data=05%7C01%7Chongxin
> g.zhu%
> >
> +40nxp.com%7C98e38ab75655406d3dea08db031176da%7C686ea1d3bc2b4
> c6fa92cd9
> >
> +9c5c301635%7C0%7C0%7C638107145768672999%7CUnknown%7CTWFpb
> GZsb3d8eyJWI
> >
> +joiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7
> C3000%
> >
> +7C%7C%7C&sdata=W3CmMca9eRsPUyYiZ6Q2HIVmmHU1QgJczGeyguLs7P8
> %3D&reserve
> > +d=0
> > +
> > +title: Freescale i.MX6 PCIe Endpoint controller
> > +
> > +maintainers:
> > + - Lucas Stach <l.stach@...gutronix.de>
> > + - Richard Zhu <hongxing.zhu@....com>
> > +
> > +description: |+
> > + This PCIe controller is based on the Synopsys DesignWare PCIe IP
> > +and
> > + thus inherits all the common properties defined in
> snps,dw-pcie-ep.yaml.
> > + The controller instances are dual mode where in they can work
> > +either in
> > + Root Port mode or Endpoint mode but one at a time.
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - fsl,imx8mm-pcie-ep
> > + - fsl,imx8mq-pcie-ep
> > + - fsl,imx8mp-pcie-ep
> > +
> > + reg:
> > + minItems: 2
> > +
> > + reg-names:
> > + items:
> > + - const: dbi
> > + - const: addr_space
> > +
> > + interrupts:
> > + items:
> > + - description: builtin eDMA interrupter.
> > +
> > + interrupt-names:
> > + items:
> > + - const: dma
> > +
> > + clocks:
> > + minItems: 3
> > + items:
> > + - description: PCIe bridge clock.
> > + - description: PCIe bus clock.
> > + - description: PCIe PHY clock.
> > + - description: Additional required clock entry for imx6sx-pcie-ep,
> > + imx8mq-pcie-ep.
> > +
> > + clock-names:
> > + minItems: 3
> > + items:
> > + - const: pcie
> > + - const: pcie_bus
> > + - enum: [ pcie_phy, pcie_aux ]
> > + - enum: [ pcie_inbound_axi, pcie_aux ]
>
> Are the clocks in endpoint mode suddenly different? I can't tell, but will
> assume so since they added here.
These clocks properties are same either the controller is in RC mode or
the Endpoint mode.
Same to powers and resets later.
>
> > +
> > + num-lanes:
> > + const: 1
>
> You shouldn't need this if it can only be 1 value.
>
i.MX8QM PCIe can support up to 2lanes device, although it is not supported
yet. So it's better to keep this property.
> > +
> > + fsl,imx7d-pcie-phy:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description: A phandle to an fsl,imx7d-pcie-phy node. Additional
> > + required properties for imx7d-pcie-ep and imx8mq-pcie-ep.
> > +
> > + power-domains:
> > + minItems: 1
> > + items:
> > + - description: The phandle pointing to the DISPLAY domain for
> > + imx6sx-pcie-ep, to PCIE_PHY power domain for imx7d-pcie-ep
> and
> > + imx8mq-pcie-ep.
> > + - description: The phandle pointing to the PCIE_PHY power
> domains
> > + for imx6sx-pcie-ep.
> > +
> > + power-domain-names:
> > + minItems: 1
> > + items:
> > + - const: pcie
> > + - const: pcie_phy
> > +
> > + resets:
> > + minItems: 2
> > + maxItems: 3
> > + description: Phandles to PCIe-related reset lines exposed by SRC
> > + IP block. Additional required by imx7d-pcie-ep and
> imx8mq-pcie-ep.
> > +
> > + reset-names:
> > + minItems: 2
> > + maxItems: 3
>
> Same question for resets.
Regarding my understands, i.MX7D and i.MX8MQ PCIe controller has one wrapper
internal PCIe PHY. And this PHY is not exposed as i.MX8MM/i.MX8MP PCIe does.
So, there are some different control logic here.
>
> > +
> > + fsl,tx-deemph-gen1:
> > + description: Gen1 De-emphasis value (optional required).
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + default: 0
> > +
> > + fsl,tx-deemph-gen2-3p5db:
> > + description: Gen2 (3.5db) De-emphasis value (optional required).
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + default: 0
> > +
> > + fsl,tx-deemph-gen2-6db:
> > + description: Gen2 (6db) De-emphasis value (optional required).
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + default: 20
> > +
> > + fsl,tx-swing-full:
> > + description: Gen2 TX SWING FULL value (optional required).
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + default: 127
> > +
> > + fsl,tx-swing-low:
> > + description: TX launch amplitude swing_low value (optional required).
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + default: 127
>
> Now we'd duplicated defining the type for all these properties...
>
> This needs to be restructured into a schema of all the common properties and
> then the host and endpoint schema can reference it. IOW, like how other
> schemas have been done.
Thanks for your advice. This is a good idea. Would derive the common properties
shared by RC and EP schema.
Best Regards
Richard
>
> Rob
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