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Date: Tue, 31 Jan 2023 16:11:01 +0530
From: Devi Priya <quic_devipriy@...cinc.com>
To: Konrad Dybcio <konrad.dybcio@...aro.org>, <agross@...nel.org>,
<andersson@...nel.org>, <robh+dt@...nel.org>,
<krzysztof.kozlowski+dt@...aro.org>, <mturquette@...libre.com>,
<sboyd@...nel.org>, <linus.walleij@...aro.org>,
<catalin.marinas@....com>, <will@...nel.org>,
<p.zabel@...gutronix.de>, <shawnguo@...nel.org>, <arnd@...db.de>,
<marcel.ziswiler@...adex.com>, <dmitry.baryshkov@...aro.org>,
<nfraprado@...labora.com>, <linux-arm-msm@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-clk@...r.kernel.org>, <linux-gpio@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>
CC: <quic_srichara@...cinc.com>, <quic_gokulsri@...cinc.com>,
<quic_sjaganat@...cinc.com>, <quic_kathirav@...cinc.com>,
<quic_arajkuma@...cinc.com>, <quic_anusha@...cinc.com>,
<quic_poovendh@...cinc.com>
Subject: Re: [PATCH V3 6/7] arm64: dts: qcom: Add ipq9574 SoC and AL02 board
support
On 1/31/2023 5:25 AM, Konrad Dybcio wrote:
>
>
> On 30.01.2023 13:55, devi priya wrote:
>> Add initial device tree support for Qualcomm IPQ9574 SoC
>> and AL02 board
>>
>> Co-developed-by: Anusha Rao <quic_anusha@...cinc.com>
>> Signed-off-by: Anusha Rao <quic_anusha@...cinc.com>
>> Co-developed-by: Poovendhan Selvaraj <quic_poovendh@...cinc.com>
>> Signed-off-by: Poovendhan Selvaraj <quic_poovendh@...cinc.com>
>> Signed-off-by: devi priya <quic_devipriy@...cinc.com>
>> ---
>> Changes in V3:
>> - Updated the order of signed-offs
>>
>> Changes in V2:
>> - Updated the node name - emmc_pins to sdc_default_state
>> - Moved the xo and sleep clock frequency to board DT
>> - Removed the pipe clock definitions
>> - Dropped clock frequency property for timer nodes
>> - Added qcom,ipq9574-sdhci compatible string
>> - Updated the copyright year to 2023
>> - Corrected the indentations
>>
>> arch/arm64/boot/dts/qcom/Makefile | 1 +
>> arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts | 78 +++++
>> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 285 +++++++++++++++++++
>> 3 files changed, 364 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>> create mode 100644 arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
>> index b0423ca3e79f..ff40e86181d4 100644
>> --- a/arch/arm64/boot/dts/qcom/Makefile
>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>> @@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c2.dtb
>> +dtb-$(CONFIG_ARCH_QCOM) += ipq9574-al02-c7.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>> new file mode 100644
>> index 000000000000..4aa06e4f63c7
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>> @@ -0,0 +1,78 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
>> +/*
>> + * IPQ9574 AL02-C7 board device tree source
>> + *
>> + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
>> + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "ipq9574.dtsi"
>> +
>> +/ {
>> + model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7";
>> + compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";
>> +
>> + aliases {
>> + serial0 = &blsp1_uart2;
>> + };
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
>> +};
>> +
>> +&blsp1_uart2 {
>> + pinctrl-0 = <&uart2_pins>;
>> + pinctrl-names = "default";
>> + status = "okay";
>> +};
>> +
>> +&sdhc_1 {
>> + pinctrl-0 = <&sdc_default_state>;
>> + pinctrl-names = "default";
>> + status = "okay";
>> +};
>> +
>> +&sleep_clk {
>> + clock-frequency = <32000>;
>> +};
>> +
>> +&tlmm {
>> + sdc_default_state: sdc-default-state {
>> + clk-pins {
>> + pins = "gpio5";
>> + function = "sdc_clk";
>> + drive-strength = <8>;
>> + bias-disable;
>> + };
>> +
>> + cmd-pins {
>> + pins = "gpio4";
>> + function = "sdc_cmd";
>> + drive-strength = <8>;
>> + bias-pull-up;
>> + };
>> +
>> + data-pins {
>> + pins = "gpio0", "gpio1", "gpio2",
>> + "gpio3", "gpio6", "gpio7",
>> + "gpio8", "gpio9";
> The second and third rows are still incorrectly indented.
okay. will correct it.
>
>> + function = "sdc_data";
>> + drive-strength = <8>;
>> + bias-pull-up;
>> + };
>> +
>> + rclk-pins {
>> + pins = "gpio10";
>> + function = "sdc_rclk";
>> + drive-strength = <8>;
>> + bias-pull-down;
>> + };
>> + };
>
> [...]
>
>> + reserved-memory {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> + tz_region: memory@...00000 {
> tz@
>
Sure
>> + reg = <0x0 0x4a600000 0x0 0x400000>;
>> + no-map;
>> + };
>> + };
>> +
>> + soc: soc@0 {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0 0 0 0xffffffff>;
>> + compatible = "simple-bus";
> compatible first, please
>
Sure, okay
>> +
>> + tlmm: pinctrl@...0000 {
>> + compatible = "qcom,ipq9574-tlmm";
>> + reg = <0x01000000 0x300000>;
>> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + gpio-ranges = <&tlmm 0 0 65>;
>> + gpio-reserved-ranges = <59 1>;
> It's reserved in the pinctrl driver, no need to do it again here.
>
Okay, got it.
>
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> +
>> + uart2_pins: uart2-state {
>> + pins = "gpio34", "gpio35";
>
> [...]
>
>> +
>> + intc: interrupt-controller@...0000 {
>> + compatible = "qcom,msm-qgic2";
>> + reg = <0x0b000000 0x1000>, /* GICD */
>> + <0x0b002000 0x1000>, /* GICC */
>> + <0x0b001000 0x1000>, /* GICH */
>> + <0x0b004000 0x1000>; /* GICV */
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + interrupt-controller;
>> + #interrupt-cells = <3>;
>> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> + ranges = <0 0x0b00c000 0x3000>;
>> +
>> + v2m0: v2m@0 {
>> + compatible = "arm,gic-v2m-frame";
>> + reg = <0x0 0xffd>;
>> + msi-controller;
>> + };
>> +
>> + v2m1: v2m@1 {
>> + compatible = "arm,gic-v2m-frame";
>> + reg = <0x00001000 0xffd>;
> Unit address must match the address part of the reg property.
>
Okay
>> + msi-controller;
>> + };
>> +
>> + v2m2: v2m@2 {
> And here.
>
Okay
> Konrad
>> + compatible = "arm,gic-v2m-frame";
>> + reg = <0x00002000 0xffd>;
>> + msi-controller;
>> + };
>> + };
>> +
>> + timer@...0000 {
>> + compatible = "arm,armv7-timer-mem";
>> + reg = <0x0b120000 0x1000>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + frame@...0000 {
>> + reg = <0x0b121000 0x1000>,
>> + <0x0b122000 0x1000>;
>> + frame-number = <0>;
>> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> +
>> + frame@...3000 {
>> + reg = <0x0b123000 0x1000>;
>> + frame-number = <1>;
>> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> + status = "disabled";
>> + };
>> +
>> + frame@...4000 {
>> + reg = <0x0b124000 0x1000>;
>> + frame-number = <2>;
>> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
>> + status = "disabled";
>> + };
>> +
>> + frame@...5000 {
>> + reg = <0x0b125000 0x1000>;
>> + frame-number = <3>;
>> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
>> + status = "disabled";
>> + };
>> +
>> + frame@...6000 {
>> + reg = <0x0b126000 0x1000>;
>> + frame-number = <4>;
>> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
>> + status = "disabled";
>> + };
>> +
>> + frame@...7000 {
>> + reg = <0x0b127000 0x1000>;
>> + frame-number = <5>;
>> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
>> + status = "disabled";
>> + };
>> +
>> + frame@...8000 {
>> + reg = <0x0b128000 0x1000>;
>> + frame-number = <6>;
>> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
>> + status = "disabled";
>> + };
>> + };
>> + };
>> +
>> + timer {
>> + compatible = "arm,armv8-timer";
>> + interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>> + };
>> +};
Best Regards,
Devi Priya
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