linux-kernel - Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree

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Date:   Wed, 1 Feb 2023 15:31:37 +0800
From:   Hal Feng <hal.feng@...rfivetech.com>
To:     Icenowy Zheng <uwu@...nowy.me>, Conor Dooley <conor@...nel.org>
CC:     <linux-riscv@...ts.infradead.org>, <devicetree@...r.kernel.org>,
        "Palmer Dabbelt" <palmer@...belt.com>,
        Rob Herring <robh+dt@...nel.org>,
        "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@...aro.org>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Ben Dooks <ben.dooks@...ive.com>,
        Daniel Lezcano <daniel.lezcano@...aro.org>,
        "Thomas Gleixner" <tglx@...utronix.de>,
        Marc Zyngier <maz@...nel.org>, Stephen Boyd <sboyd@...nel.org>,
        Michael Turquette <mturquette@...libre.com>,
        "Philipp Zabel" <p.zabel@...gutronix.de>,
        Linus Walleij <linus.walleij@...aro.org>,
        Emil Renner Berthing <emil.renner.berthing@...onical.com>,
        <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110
 device tree

On Thu, 29 Dec 2022 13:25:00 +0800, Icenowy Zheng wrote:
> 在 2022-12-28星期三的 22:48 +0000，Conor Dooley写道：
>> Hey,
>> 
>> On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
[...]
>> > +               U74_1: cpu@1 {
>> > +                       compatible = "sifive,u74-mc", "riscv";
>> > +                       reg = <1>;
>> > +                       d-cache-block-size = <64>;
>> > +                       d-cache-sets = <64>;
>> > +                       d-cache-size = <32768>;
>> > +                       d-tlb-sets = <1>;
>> > +                       d-tlb-size = <40>;
>> > +                       device_type = "cpu";
>> > +                       i-cache-block-size = <64>;
>> > +                       i-cache-sets = <64>;
>> > +                       i-cache-size = <32768>;
>> > +                       i-tlb-sets = <1>;
>> > +                       i-tlb-size = <40>;
>> > +                       mmu-type = "riscv,sv39";
>> > +                       next-level-cache = <&ccache>;
>> > +                       riscv,isa = "rv64imafdc";
>> 
>> That also begs the question:
>> Do your u74s support RV64GBC, as the (current) SiFive documentation
>> suggests?
> 
> It supports RV64GCZbaZbb.
> 
> B is not a well-defined thing by specifications, so it should be
> prevented here.

Thank you for your kindly reply.

Best regards,
Hal