linux-kernel - Re: [PATCH V4 6/7] arm64: dts: qcom: Add ipq9574 SoC and AL02 board support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <8dbdc5c2-58a3-32b8-5583-b216ae51ec95@quicinc.com>
Date:   Wed, 1 Feb 2023 16:16:46 +0530
From:   Devi Priya <quic_devipriy@...cinc.com>
To:     Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
        <agross@...nel.org>, <andersson@...nel.org>,
        <konrad.dybcio@...aro.org>, <robh+dt@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>, <mturquette@...libre.com>,
        <sboyd@...nel.org>, <linus.walleij@...aro.org>,
        <catalin.marinas@....com>, <will@...nel.org>,
        <p.zabel@...gutronix.de>, <shawnguo@...nel.org>, <arnd@...db.de>,
        <marcel.ziswiler@...adex.com>, <dmitry.baryshkov@...aro.org>,
        <nfraprado@...labora.com>, <broonie@...nel.org>,
        <linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <linux-clk@...r.kernel.org>,
        <linux-gpio@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>
CC:     <quic_srichara@...cinc.com>, <quic_gokulsri@...cinc.com>,
        <quic_sjaganat@...cinc.com>, <quic_kathirav@...cinc.com>,
        <quic_arajkuma@...cinc.com>, <quic_anusha@...cinc.com>,
        <quic_poovendh@...cinc.com>
Subject: Re: [PATCH V4 6/7] arm64: dts: qcom: Add ipq9574 SoC and AL02 board
 support



On 2/1/2023 1:07 PM, Krzysztof Kozlowski wrote:
> On 01/02/2023 07:03, Devi Priya wrote:
>> Add initial device tree support for Qualcomm IPQ9574 SoC and AL02 board
>>
>> Co-developed-by: Anusha Rao <quic_anusha@...cinc.com>
>> Signed-off-by: Anusha Rao <quic_anusha@...cinc.com>
>> Co-developed-by: Poovendhan Selvaraj <quic_poovendh@...cinc.com>
>> Signed-off-by: Poovendhan Selvaraj <quic_poovendh@...cinc.com>
>> Signed-off-by: Devi Priya <quic_devipriy@...cinc.com>
>> ---
> 
> 
>> +
>> +		sdhc_1: mmc@...4000 {
>> +			compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5";
>> +			reg = <0x07804000 0x1000>, <0x07805000 0x1000>;
>> +			reg-names = "hc", "cqhci";
>> +
>> +			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
>> +			interrupt-names = "hc_irq", "pwr_irq";
>> +
>> +			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
>> +				 <&gcc GCC_SDCC1_APPS_CLK>,
>> +				 <&xo_board_clk>;
>> +			clock-names = "iface", "core", "xo";
>> +			mmc-ddr-1_8v;
>> +			mmc-hs200-1_8v;
>> +			mmc-hs400-1_8v;
>> +			mmc-hs400-enhanced-strobe;
>> +			max-frequency = <384000000>;
>> +			bus-width = <8>;
> 
> None of these 6 are properties of the SoC. Move them to the DTS.
> 
Sure, will do

> Best regards,
> Krzysztof
> 
Best Regards,
Devi Priya