linux-kernel - Re: [PATCH v2 8/9] arm64: dts: qcom: ipq8074: fix Gen3 PCIe node

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Thu, 02 Feb 2023 10:42:15 +0100
From:   "Arnd Bergmann" <arnd@...db.de>
To:     "Robert Marko" <robimarko@...il.com>
Cc:     "Andy Gross" <agross@...nel.org>,
        "Bjorn Andersson" <andersson@...nel.org>,
        "Konrad Dybcio" <konrad.dybcio@...aro.org>, bhelgaas@...gle.com,
        lpieralisi@...nel.org, "Rob Herring" <robh@...nel.org>,
        Krzysztof Wilczyński <kw@...ux.com>,
        krzysztof.kozlowski+dt@...aro.org,
        "Manivannan Sadhasivam" <mani@...nel.org>, svarbanov@...sol.com,
        shawn.guo@...aro.org, linux-arm-msm@...r.kernel.org,
        linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, "Abel Vesa" <abelvesa@...nel.org>,
        "Jingoo Han" <jingoohan1@...il.com>,
        "Gustavo Pimentel" <gustavo.pimentel@...opsys.com>,
        linux-pci@...r.kernel.org
Subject: Re: [PATCH v2 8/9] arm64: dts: qcom: ipq8074: fix Gen3 PCIe node

On Thu, Feb 2, 2023, at 10:16, Robert Marko wrote:
> On Mon, 30 Jan 2023 at 18:11, Arnd Bergmann <arnd@...db.de> wrote:
>> On Fri, Jan 13, 2023, at 17:44, Robert Marko wrote:
>
> As pointed out in the commit description, the ranges property was copied
> from the QCA-s downstream 5.4 kernel [1] as I dont have any documentation
> on the SoC.
>
> I have runtime tested this on Xiaomi AX3600 which has a QCA9889 card on the
> Gen3 PCIe port, and on Xiaomi AX9000 which has QCA9889 on Gen2 port
> and QCN9074 on the Gen3 port and they are working fine.

Neither of those use I/O ports though, nor does any other sensible
device that was made in the past decade.

The compatible string tells me that this is a designware pcie block,
so I think driver actually sets up the mapping based on the ranges
property in DT in dw_pcie_iatu_detect() and dw_pcie_iatu_setup(),
rather than the mapping being determined by hardware or firmware
in advance.

Not sure about the general policy we have for this case, maybe the
pci controller or pci-dwc maintainers have an idea here. I would
think it's better to either have no I/O ranges in DT or have
sensible ones than ones that are clearly bogus, if the controller
is able to set up the ranges.

     Arnd