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Date: Thu, 2 Feb 2023 11:33:53 +0000
From: Conor Dooley <conor.dooley@...rochip.com>
To: Atish Patra <atishp@...osinc.com>
CC: <linux-kernel@...r.kernel.org>, Albert Ou <aou@...s.berkeley.edu>,
Andrew Jones <ajones@...tanamicro.com>,
Anup Patel <anup@...infault.org>,
Atish Patra <atishp@...shpatra.org>,
Eric Lin <eric.lin@...ive.com>, Guo Ren <guoren@...nel.org>,
Heiko Stuebner <heiko@...ech.de>,
<kvm-riscv@...ts.infradead.org>, <kvm@...r.kernel.org>,
<linux-riscv@...ts.infradead.org>,
Mark Rutland <mark.rutland@....com>,
Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Will Deacon <will@...nel.org>
Subject: Re: [PATCH v4 07/14] RISC-V: KVM: Add skeleton support for perf
On Wed, Feb 01, 2023 at 03:12:43PM -0800, Atish Patra wrote:
> This patch only adds barebone structure of perf implementation. Most of
> the function returns zero at this point and will be implemented
> fully in the future.
>
> Signed-off-by: Atish Patra <atishp@...osinc.com>
> +/* Per virtual pmu counter data */
> +struct kvm_pmc {
> + u8 idx;
> + struct perf_event *perf_event;
> + uint64_t counter_val;
CI also complained that here, and elsewhere, you used uint64_t rather
than u64. Am I missing a reason for not using the regular types?
Thanks,
Conor.
> + union sbi_pmu_ctr_info cinfo;
> + /* Event monitoring status */
> + bool started;
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