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Message-ID: <167559659472.4906.2586833215028000234.tip-bot2@tip-bot2>
Date: Sun, 05 Feb 2023 11:29:54 -0000
From: "irqchip-bot for Huacai Chen" <tip-bot2@...utronix.de>
To: linux-kernel@...r.kernel.org
Cc: Yingkun Meng <mengyingkun@...ngson.cn>,
Huacai Chen <chenhuacai@...ngson.cn>,
Marc Zyngier <maz@...nel.org>, tglx@...utronix.de
Subject: [irqchip: irq/irqchip-next] irqchip/loongson-liointc: Save/restore
int_edge/int_pol registers during S3/S4
The following commit has been merged into the irq/irqchip-next branch of irqchip:
Commit-ID: fc98adb9a8435cdb4e8349138ac0b728df80ade9
Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/fc98adb9a8435cdb4e8349138ac0b728df80ade9
Author: Huacai Chen <chenhuacai@...ngson.cn>
AuthorDate: Wed, 07 Dec 2022 22:06:43 +08:00
Committer: Marc Zyngier <maz@...nel.org>
CommitterDate: Sun, 05 Feb 2023 10:55:19
irqchip/loongson-liointc: Save/restore int_edge/int_pol registers during S3/S4
If int_edge/int_pol registers are configured to not be the default values, we
should save/restore them during S3/S4.
Signed-off-by: Yingkun Meng <mengyingkun@...ngson.cn>
Signed-off-by: Huacai Chen <chenhuacai@...ngson.cn>
Signed-off-by: Marc Zyngier <maz@...nel.org>
Link: https://lore.kernel.org/r/20221207140643.1600743-1-chenhuacai@loongson.cn
---
drivers/irqchip/irq-loongson-liointc.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
index 85b754f..8d00a9a 100644
--- a/drivers/irqchip/irq-loongson-liointc.c
+++ b/drivers/irqchip/irq-loongson-liointc.c
@@ -55,6 +55,8 @@ struct liointc_priv {
struct liointc_handler_data handler[LIOINTC_NUM_PARENT];
void __iomem *core_isr[LIOINTC_NUM_CORES];
u8 map_cache[LIOINTC_CHIP_IRQ];
+ u32 int_pol;
+ u32 int_edge;
bool has_lpc_irq_errata;
};
@@ -138,6 +140,14 @@ static int liointc_set_type(struct irq_data *data, unsigned int type)
return 0;
}
+static void liointc_suspend(struct irq_chip_generic *gc)
+{
+ struct liointc_priv *priv = gc->private;
+
+ priv->int_pol = readl(gc->reg_base + LIOINTC_REG_INTC_POL);
+ priv->int_edge = readl(gc->reg_base + LIOINTC_REG_INTC_EDGE);
+}
+
static void liointc_resume(struct irq_chip_generic *gc)
{
struct liointc_priv *priv = gc->private;
@@ -150,6 +160,8 @@ static void liointc_resume(struct irq_chip_generic *gc)
/* Restore map cache */
for (i = 0; i < LIOINTC_CHIP_IRQ; i++)
writeb(priv->map_cache[i], gc->reg_base + i);
+ writel(priv->int_pol, gc->reg_base + LIOINTC_REG_INTC_POL);
+ writel(priv->int_edge, gc->reg_base + LIOINTC_REG_INTC_EDGE);
/* Restore mask cache */
writel(gc->mask_cache, gc->reg_base + LIOINTC_REG_INTC_ENABLE);
irq_gc_unlock_irqrestore(gc, flags);
@@ -269,6 +281,7 @@ static int liointc_init(phys_addr_t addr, unsigned long size, int revision,
gc->private = priv;
gc->reg_base = base;
gc->domain = domain;
+ gc->suspend = liointc_suspend;
gc->resume = liointc_resume;
ct = gc->chip_types;
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