[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <86357k1ihd.wl-maz@kernel.org>
Date: Sun, 05 Feb 2023 11:04:14 +0000
From: Marc Zyngier <maz@...nel.org>
To: Anup Patel <apatel@...tanamicro.com>
Cc: Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Thomas Gleixner <tglx@...utronix.de>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Hector Martin <marcan@...can.st>,
Sven Peter <sven@...npeter.dev>,
Alyssa Rosenzweig <alyssa@...enzweig.io>,
Atish Patra <atishp@...shpatra.org>,
Alistair Francis <Alistair.Francis@....com>,
Anup Patel <anup@...infault.org>,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
asahi@...ts.linux.dev
Subject: Re: [PATCH v16 0/9] RISC-V IPI Improvements
On Tue, 03 Jan 2023 14:12:12 +0000,
Anup Patel <apatel@...tanamicro.com> wrote:
>
> This series aims to improve IPI support in Linux RISC-V in following ways:
> 1) Treat IPIs as normal per-CPU interrupts instead of having custom RISC-V
> specific hooks. This also makes Linux RISC-V IPI support aligned with
> other architectures.
> 2) Remote TLB flushes and icache flushes should prefer local IPIs instead
> of SBI calls whenever we have specialized hardware (such as RISC-V AIA
> IMSIC and RISC-V SWI) which allows S-mode software to directly inject
> IPIs without any assistance from M-mode runtime firmware.
[...]
I'm queuing patches 3 and 9 via the irqchip tree as they are
standalone.
For the rest, I need an Ack from the riscv maintainers as they change
a large amount of arch-specific code, and the couple of irqchip
patches depend on these changes.
Palmer, Paul?
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
Powered by blists - more mailing lists