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Message-ID: <CADnq5_OAZ2-sKs8Cr3=t3SjMT9NoGBFRbh2Jtzpy60x_5xsKCQ@mail.gmail.com>
Date: Mon, 6 Feb 2023 15:24:39 -0500
From: Alex Deucher <alexdeucher@...il.com>
To: Arnd Bergmann <arnd@...nel.org>
Cc: Harry Wentland <harry.wentland@....com>,
Leo Li <sunpeng.li@....com>,
Rodrigo Siqueira <Rodrigo.Siqueira@....com>,
Aric Cyr <aric.cyr@....com>, Arnd Bergmann <arnd@...db.de>,
"Pan, Xinhui" <Xinhui.Pan@....com>, linux-kernel@...r.kernel.org,
amd-gfx@...ts.freedesktop.org,
Dmytro Laktyushkin <Dmytro.Laktyushkin@....com>,
Nevenko Stupar <Nevenko.Stupar@....com>,
dri-devel@...ts.freedesktop.org, Daniel Vetter <daniel@...ll.ch>,
Alex Deucher <alexander.deucher@....com>,
Yang Li <yang.lee@...ux.alibaba.com>,
Jun Lei <Jun.Lei@....com>, David Airlie <airlied@...il.com>,
Christian König <christian.koenig@....com>,
Pavle Kotarac <Pavle.Kotarac@....com>
Subject: Re: [PATCH] [SUBMITTED 20210927] [RESEND^2] drm/amdgpu: fix enum
odm_combine_mode mismatch
On Mon, Feb 6, 2023 at 2:36 PM Arnd Bergmann <arnd@...nel.org> wrote:
>
> From: Arnd Bergmann <arnd@...db.de>
>
> A conversion from 'bool' to 'enum odm_combine_mode' was incomplete,
> and gcc warns about this with many instances of
>
> display/dc/dml/dcn20/display_mode_vba_20.c:3899:44: warning: implicit conversion from 'enum <anonymous>' to 'enum
> odm_combine_mode' [-Wenum-conversion]
> 3899 | locals->ODMCombineEnablePerState[i][k] = false;
>
> Change the ones that we get a warning for, using the same numerical
> values to leave the behavior unchanged.
>
> Fixes: 5fc11598166d ("drm/amd/display: expand dml structs")
> Link: https://lore.kernel.org/all/20201026210039.3884312-3-arnd@kernel.org/
> Link: https://lore.kernel.org/all/20210927100659.1431744-1-arnd@kernel.org/
> Signed-off-by: Arnd Bergmann <arnd@...db.de>
> ---
> I sent this in 2020 and in 2021, but never got a reply and the warning
> is still there.
Applied. Sorry for the delay.
Alex
> ---
> .../amd/display/dc/dml/dcn20/display_mode_vba_20.c | 8 ++++----
> .../amd/display/dc/dml/dcn20/display_mode_vba_20v2.c | 10 +++++-----
> .../amd/display/dc/dml/dcn21/display_mode_vba_21.c | 12 ++++++------
> 3 files changed, 15 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
> index f34bc3c8da41..69c41e3e3ba2 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
> @@ -3901,14 +3901,14 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
> mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2
> * (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
>
> - locals->ODMCombineEnablePerState[i][k] = false;
> + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
> mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine;
> if (mode_lib->vba.ODMCapability) {
> if (locals->PlaneRequiredDISPCLKWithoutODMCombine > mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity) {
> - locals->ODMCombineEnablePerState[i][k] = true;
> + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
> mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
> } else if (locals->HActive[k] > DCN20_MAX_420_IMAGE_WIDTH && locals->OutputFormat[k] == dm_420) {
> - locals->ODMCombineEnablePerState[i][k] = true;
> + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
> mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
> }
> }
> @@ -3961,7 +3961,7 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
> locals->RequiredDISPCLK[i][j] = 0.0;
> locals->DISPCLK_DPPCLK_Support[i][j] = true;
> for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
> - locals->ODMCombineEnablePerState[i][k] = false;
> + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
> if (locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]) {
> locals->NoOfDPP[i][j][k] = 1;
> locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k]
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
> index 366138df0fe2..f475a0ae946c 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
> @@ -4012,17 +4012,17 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode
> mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2
> * (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
>
> - locals->ODMCombineEnablePerState[i][k] = false;
> + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
> mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine;
> if (mode_lib->vba.ODMCapability) {
> if (locals->PlaneRequiredDISPCLKWithoutODMCombine > MaxMaxDispclkRoundedDown) {
> - locals->ODMCombineEnablePerState[i][k] = true;
> + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
> mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
> } else if (locals->DSCEnabled[k] && (locals->HActive[k] > DCN20_MAX_DSC_IMAGE_WIDTH)) {
> - locals->ODMCombineEnablePerState[i][k] = true;
> + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
> mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
> } else if (locals->HActive[k] > DCN20_MAX_420_IMAGE_WIDTH && locals->OutputFormat[k] == dm_420) {
> - locals->ODMCombineEnablePerState[i][k] = true;
> + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
> mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
> }
> }
> @@ -4075,7 +4075,7 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode
> locals->RequiredDISPCLK[i][j] = 0.0;
> locals->DISPCLK_DPPCLK_Support[i][j] = true;
> for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
> - locals->ODMCombineEnablePerState[i][k] = false;
> + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
> if (locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]) {
> locals->NoOfDPP[i][j][k] = 1;
> locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k]
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
> index eeb4d3441e1d..3a896d0172a9 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
> @@ -4106,17 +4106,17 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
> mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2
> * (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
>
> - locals->ODMCombineEnablePerState[i][k] = false;
> + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
> mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine;
> if (mode_lib->vba.ODMCapability) {
> if (locals->PlaneRequiredDISPCLKWithoutODMCombine > MaxMaxDispclkRoundedDown) {
> - locals->ODMCombineEnablePerState[i][k] = true;
> + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
> mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
> } else if (locals->DSCEnabled[k] && (locals->HActive[k] > DCN21_MAX_DSC_IMAGE_WIDTH)) {
> - locals->ODMCombineEnablePerState[i][k] = true;
> + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
> mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
> } else if (locals->HActive[k] > DCN21_MAX_420_IMAGE_WIDTH && locals->OutputFormat[k] == dm_420) {
> - locals->ODMCombineEnablePerState[i][k] = true;
> + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
> mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
> }
> }
> @@ -4169,7 +4169,7 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
> locals->RequiredDISPCLK[i][j] = 0.0;
> locals->DISPCLK_DPPCLK_Support[i][j] = true;
> for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
> - locals->ODMCombineEnablePerState[i][k] = false;
> + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
> if (locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]) {
> locals->NoOfDPP[i][j][k] = 1;
> locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k]
> @@ -5234,7 +5234,7 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
> mode_lib->vba.ODMCombineEnabled[k] =
> locals->ODMCombineEnablePerState[mode_lib->vba.VoltageLevel][k];
> } else {
> - mode_lib->vba.ODMCombineEnabled[k] = false;
> + mode_lib->vba.ODMCombineEnabled[k] = dm_odm_combine_mode_disabled;
> }
> mode_lib->vba.DSCEnabled[k] =
> locals->RequiresDSC[mode_lib->vba.VoltageLevel][k];
> --
> 2.39.0
>
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