linux-kernel - [PATCH RFC 00/12] RISC-V: support some cryptography accelerations

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Message-Id: <20230206225846.1381789-1-heiko@sntech.de>
Date:   Mon,  6 Feb 2023 23:58:34 +0100
From:   Heiko Stuebner <heiko@...ech.de>
To:     palmer@...osinc.com
Cc:     greentime.hu@...ive.com, conor@...nel.org,
        linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
        christoph.muellner@...ll.eu,
        Heiko Stuebner <heiko.stuebner@...ll.eu>
Subject: [PATCH RFC 00/12] RISC-V: support some cryptography accelerations

From: Heiko Stuebner <heiko.stuebner@...ll.eu>

So this was my playground the last days.

The base is v13 of the vector patchset but the first patches up to doing
the Zbc-based GCM GHash can also run without those. Of course the vector-
crypto extensions are also not ratified yet, hence the marking as RFC.


As v13 of the vector patchset dropped the patches for in-kernel usage of
vector instructions, I picked the ones from v12 over into this series
for now.

My basic goal was to not re-invent cryptographic code, so the heavy
lifting is done by those perl-asm scripts used in openssl and the perl
code used here-in stems from code that is targetted at openssl [0] and is
unmodified from there to limit needed review effort.


With a matching qemu (there are patches for vector-crypto flying around)
the in-kernel crypto-selftests (also the extended ones) are very happy
so far.


Things to do:
- The series still includes its own Zbb extension detection,
  I'll need to untangle my branches to adapt to the applied Zbb
  patchset [and address Andrews comments]
- use correct Co-developed-attribution for the code coming from
  openssl
- some more cryptographic algorithms (aes, sha512, sm3, sm4)


[0] both still open
https://github.com/openssl/openssl/pull/20078
https://github.com/openssl/openssl/pull/20149


Greentime Hu (2):
  riscv: Add support for kernel mode vector
  riscv: Add vector extension XOR implementation

Heiko Stuebner (10):
  RISC-V: add Zbb extension detection
  RISC-V: add Zbc extension detection
  RISC-V: add Zbkb extension detection
  RISC-V: hook new crypto subdir into build-system
  RISC-V: crypto: add accelerated GCM GHASH implementation
  RISC-V: add vector crypto extension detection
  RISC-V: crypto: update perl include with helpers for vector (crypto)
    instructions
  RISC-V: crypto: add Zvkb accelerated GCM GHASH implementation
  RISC-V: crypto: add Zvkg accelerated GCM GHASH implementation
  RISC-V: crypto: add a vector-crypto-accelerated SHA256 implementation

 arch/riscv/Kbuild                          |   1 +
 arch/riscv/Kconfig                         |  45 ++
 arch/riscv/crypto/Kconfig                  |  28 +
 arch/riscv/crypto/Makefile                 |  34 +
 arch/riscv/crypto/ghash-riscv64-glue.c     | 489 ++++++++++++++
 arch/riscv/crypto/ghash-riscv64-zbc.pl     | 400 ++++++++++++
 arch/riscv/crypto/ghash-riscv64-zvkb.pl    | 346 ++++++++++
 arch/riscv/crypto/ghash-riscv64-zvkg.pl    | 172 +++++
 arch/riscv/crypto/riscv.pm                 | 723 +++++++++++++++++++++
 arch/riscv/crypto/sha256-riscv64-glue.c    | 103 +++
 arch/riscv/crypto/sha256-riscv64-zvknha.pl | 502 ++++++++++++++
 arch/riscv/include/asm/hwcap.h             |   7 +
 arch/riscv/include/asm/vector.h            |  14 +
 arch/riscv/include/asm/xor.h               |  82 +++
 arch/riscv/kernel/Makefile                 |   1 +
 arch/riscv/kernel/cpu.c                    |   7 +
 arch/riscv/kernel/cpufeature.c             |   7 +
 arch/riscv/kernel/kernel_mode_vector.c     | 132 ++++
 arch/riscv/lib/Makefile                    |   1 +
 arch/riscv/lib/xor.S                       |  81 +++
 crypto/Kconfig                             |   3 +
 21 files changed, 3178 insertions(+)
 create mode 100644 arch/riscv/crypto/Kconfig
 create mode 100644 arch/riscv/crypto/Makefile
 create mode 100644 arch/riscv/crypto/ghash-riscv64-glue.c
 create mode 100644 arch/riscv/crypto/ghash-riscv64-zbc.pl
 create mode 100644 arch/riscv/crypto/ghash-riscv64-zvkb.pl
 create mode 100644 arch/riscv/crypto/ghash-riscv64-zvkg.pl
 create mode 100644 arch/riscv/crypto/riscv.pm
 create mode 100644 arch/riscv/crypto/sha256-riscv64-glue.c
 create mode 100644 arch/riscv/crypto/sha256-riscv64-zvknha.pl
 create mode 100644 arch/riscv/include/asm/xor.h
 create mode 100644 arch/riscv/kernel/kernel_mode_vector.c
 create mode 100644 arch/riscv/lib/xor.S

-- 
2.39.0