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Message-Id: <20230206100105.861720-1-angelogioacchino.delregno@collabora.com>
Date: Mon, 6 Feb 2023 11:00:58 +0100
From: AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>
To: sboyd@...nel.org
Cc: mturquette@...libre.com, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, matthias.bgg@...il.com,
angelogioacchino.delregno@...labora.com,
edward-jw.yang@...iatek.com, johnson.wang@...iatek.com,
wenst@...omium.org, miles.chen@...iatek.com,
chun-jie.chen@...iatek.com, rex-bc.chen@...iatek.com,
jose.exposito89@...il.com, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org, linux-kernel@...r.kernel.org,
kernel@...labora.com
Subject: [PATCH v3 0/7] MediaTek Frequency Hopping: MT6795/8173/92/95
Changes in v3:
- Added commit to export register/unregister/parse FHCTL functions
to allow building clock drivers using FHCTL as modules
Changes in v2:
- Rebased over v4 of my clock drivers cleanups series [1]
This series adds support for Frequency Hopping (FHCTL) on more MediaTek
SoCs, specifically, MT6795, MT8173, MT8192 and MT8195.
In order to support older platforms like MT6795 and MT8173 it was
necessary to add a new register layout that is ever-so-slightly
different from the one that was previously introduced for MT8186.
Since the new layout refers to older SoCs, the one valid for MT8186
and newer SoCs was renamed to be a "v2" layout, while the new one
for older chips gets the "v1" name.
Note: These commits won't change any behavior unless FHCTL gets
explicitly enabled and configured in devicetrees.
[1]: https://patchwork.kernel.org/project/linux-mediatek/list/?series=714059
AngeloGioacchino Del Regno (7):
clk: mediatek: fhctl: Add support for older fhctl register layout
clk: mediatek: clk-pllfh: Export register/unregister/parse functions
dt-bindings: clock: mediatek,mt8186-fhctl: Support MT6795,
MT8173/92/95
clk: mediatek: mt6795: Add support for frequency hopping through FHCTL
clk: mediatek: mt8173: Add support for frequency hopping through FHCTL
clk: mediatek: mt8192: Add support for frequency hopping through FHCTL
clk: mediatek: mt8195: Add support for frequency hopping through FHCTL
.../bindings/clock/mediatek,mt8186-fhctl.yaml | 7 +-
drivers/clk/mediatek/clk-fhctl.c | 26 ++++++-
drivers/clk/mediatek/clk-fhctl.h | 9 ++-
drivers/clk/mediatek/clk-mt6795-apmixedsys.c | 63 ++++++++++++++++-
drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 65 ++++++++++++++++-
drivers/clk/mediatek/clk-mt8186-apmixedsys.c | 2 +
drivers/clk/mediatek/clk-mt8192.c | 67 +++++++++++++++++-
drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 69 ++++++++++++++++++-
drivers/clk/mediatek/clk-pllfh.c | 26 +++++--
drivers/clk/mediatek/clk-pllfh.h | 1 +
10 files changed, 314 insertions(+), 21 deletions(-)
--
2.39.1
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