[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20230206113811.23133-4-walker.chen@starfivetech.com>
Date: Mon, 6 Feb 2023 19:38:11 +0800
From: Walker Chen <walker.chen@...rfivetech.com>
To: <linux-riscv@...ts.infradead.org>, <dmaengine@...r.kernel.org>,
<devicetree@...r.kernel.org>
CC: Eugeniy Paltsev <Eugeniy.Paltsev@...opsys.com>,
Vinod Koul <vkoul@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor@...nel.org>,
"Palmer Dabbelt" <palmer@...belt.com>,
Emil Renner Berthing <kernel@...il.dk>,
"Walker Chen" <walker.chen@...rfivetech.com>,
<linux-kernel@...r.kernel.org>
Subject: [PATCH v1 3/3] riscv: dts: starfive: add dma controller node
Adding the dma controller node for the Starfive JH7110 SoC.
Signed-off-by: Walker Chen <walker.chen@...rfivetech.com>
---
arch/riscv/boot/dts/starfive/jh7110.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index cfbaff4ea64b..1628c0f33fab 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -412,6 +412,26 @@
#gpio-cells = <2>;
};
+ dma: dma-controller@...50000 {
+ compatible = "starfive,axi-dma";
+ reg = <0x0 0x16050000 0x0 0x10000>;
+ clocks = <&stgcrg JH7110_STGCLK_DMA1P_AXI>,
+ <&stgcrg JH7110_STGCLK_DMA1P_AHB>;
+ clock-names = "core-clk", "cfgr-clk";
+ resets = <&stgcrg JH7110_STGRST_DMA1P_AXI>,
+ <&stgcrg JH7110_STGRST_DMA1P_AHB>;
+ reset-names = "axi-rst", "ahb-rst";
+ interrupts = <73>;
+ #dma-cells = <1>;
+ dma-channels = <4>;
+ snps,dma-masters = <1>;
+ snps,data-width = <3>;
+ snps,num-hs-if = <56>;
+ snps,block-size = <65536 65536 65536 65536>;
+ snps,priority = <0 1 2 3>;
+ snps,axi-max-burst-len = <16>;
+ };
+
aoncrg: clock-controller@...00000 {
compatible = "starfive,jh7110-aoncrg";
reg = <0x0 0x17000000 0x0 0x10000>;
--
2.17.1
Powered by blists - more mailing lists