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Message-Id: <1675743508-24702-3-git-send-email-hongxing.zhu@nxp.com>
Date: Tue, 7 Feb 2023 12:18:26 +0800
From: Richard Zhu <hongxing.zhu@....com>
To: robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
l.stach@...gutronix.de, shawnguo@...nel.org,
lorenzo.pieralisi@....com, peng.fan@....com, marex@...x.de,
marcel.ziswiler@...adex.com, tharvey@...eworks.com,
frank.li@....com
Cc: hongxing.zhu@....com, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
kernel@...gutronix.de, linux-imx@....com
Subject: [PATCH v10 2/4] arm64: dts: Add i.MX8MM PCIe EP support
Add i.MX8MM PCIe EP support.
Signed-off-by: Richard Zhu <hongxing.zhu@....com>
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 24 +++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 31f4548f85cf..a9552867e547 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1315,6 +1315,30 @@ pcie0: pcie@...00000 {
status = "disabled";
};
+ pcie0_ep: pcie-ep@...00000 {
+ compatible = "fsl,imx8mm-pcie-ep";
+ reg = <0x33800000 0x400000>,
+ <0x18000000 0x8000000>;
+ reg-names = "dbi", "addr_space";
+ num-lanes = <1>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dma";
+ fsl,max-link-speed = <2>;
+ clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
+ <&clk IMX8MM_CLK_PCIE1_PHY>,
+ <&clk IMX8MM_CLK_PCIE1_AUX>;
+ clock-names = "pcie", "pcie_bus", "pcie_aux";
+ power-domains = <&pgc_pcie>;
+ resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
+ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
+ reset-names = "apps", "turnoff";
+ phys = <&pcie_phy>;
+ phy-names = "pcie-phy";
+ num-ib-windows = <4>;
+ num-ob-windows = <4>;
+ status = "disabled";
+ };
+
gpu_3d: gpu@...00000 {
compatible = "vivante,gc";
reg = <0x38000000 0x8000>;
--
2.34.1
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