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Message-ID: <ee69c345-f4eb-bb35-4825-f23b44faadbc@linux.alibaba.com>
Date:   Wed, 8 Feb 2023 11:43:19 +0800
From:   Carlo Bai <carlo.bai@...ux.alibaba.com>
To:     Catalin Marinas <catalin.marinas@....com>
Cc:     will@...nel.org, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org, anshuman.khandual@....com,
        baolin.wang@...ux.alibaba.com
Subject: Re: [RFC PATCH 1/1] arm64: mm: remove unnecessary multiple tlb flush
 of contiguous hugetlb

On 2023/2/8 2:21, Catalin Marinas wrote:
> On Tue, Feb 07, 2023 at 07:09:41PM +0800, Kaihao Bai wrote:
>> In arm64, contiguous flag refers to the same TLB entry that shared by a
>> contiguous address range. If flush one entry of the address range, it
>> would cover the whole contiguous address range. Thus there's no need to
>> flush all contiguous range that CONT_PMD/PTE points to.
> 
> This doesn't work. The contiguous bit is a hint, so the CPU may not
> coalesce multiple PTEs into a single TLB entry.
>Sorry I misunderstood the underlying approach of contiguous bit. I 
re-check and find that "TLB maintenance must be performed based on the 
size of the underlying translation table entries, to avoid TLB
coherency issues.". Thanks for your clarification!

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