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Message-ID: <dbc93125-afd5-9ed9-7b45-0d79f728b4a5@linaro.org>
Date: Wed, 8 Feb 2023 08:59:07 +0100
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Poovendhan Selvaraj <quic_poovendh@...cinc.com>, agross@...nel.org,
andersson@...nel.org, konrad.dybcio@...aro.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, lee@...nel.org,
mturquette@...libre.com, sboyd@...nel.org,
jassisinghbrar@...il.com, catalin.marinas@....com, will@...nel.org,
shawnguo@...nel.org, arnd@...db.de, marcel.ziswiler@...adex.com,
robimarko@...il.com, dmitry.baryshkov@...aro.org,
nfraprado@...labora.com, broonie@...nel.org,
quic_gurus@...cinc.com, linux-arm-msm@...r.kernel.org,
linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Cc: quic_srichara@...cinc.com, quic_gokulsri@...cinc.com,
quic_sjaganat@...cinc.com, quic_kathirav@...cinc.com,
quic_arajkuma@...cinc.com, quic_anusha@...cinc.com,
quic_devipriy@...cinc.com
Subject: Re: [PATCH V3 2/5] arm64: dts: qcom: Add support for Crashdump
collection on IPQ9574
On 08/02/2023 06:33, Poovendhan Selvaraj wrote:
> Enable Crashdump collection in ipq9574
>
> Co-developed-by: Anusha Rao <quic_anusha@...cinc.com>
> Signed-off-by: Anusha Rao <quic_anusha@...cinc.com>
> Co-developed-by: Kathiravan Thirumoorthy <quic_kathirav@...cinc.com>
> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@...cinc.com>
> Signed-off-by: Poovendhan Selvaraj <quic_poovendh@...cinc.com>
> ---
> Changes in V3:
> - No changes
> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 26 +++++++++++++++++++++++++-
> 1 file changed, 25 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> index 2b86ba17bb32..9c4523f50a57 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> @@ -81,6 +81,13 @@
> reg = <0x0 0x40000000 0x0 0x0>;
> };
>
> + firmware {
> + scm {
> + compatible = "qcom,scm-ipq9574", "qcom,scm";
> + qcom,dload-mode = <&tcsr_boot_misc 0>;
> + };
> + };
> +
> pmu {
> compatible = "arm,cortex-a73-pmu";
> interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> @@ -95,11 +102,17 @@
> #address-cells = <2>;
> #size-cells = <2>;
> ranges;
> -
I don't think anything improved here - still unrelated change.
Best regards,
Krzysztof
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