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Message-ID: <aadb5fb5-5aa8-fdc0-68e6-7a716073756e@quicinc.com>
Date: Wed, 8 Feb 2023 15:10:40 +0530
From: Devi Priya <quic_devipriy@...cinc.com>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
<agross@...nel.org>, <andersson@...nel.org>,
<konrad.dybcio@...aro.org>, <robh+dt@...nel.org>,
<krzysztof.kozlowski+dt@...aro.org>, <mturquette@...libre.com>,
<sboyd@...nel.org>, <linus.walleij@...aro.org>,
<catalin.marinas@....com>, <will@...nel.org>,
<p.zabel@...gutronix.de>, <shawnguo@...nel.org>, <arnd@...db.de>,
<marcel.ziswiler@...adex.com>, <nfraprado@...labora.com>,
<broonie@...nel.org>, <linux-arm-msm@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-clk@...r.kernel.org>, <linux-gpio@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>
CC: <quic_srichara@...cinc.com>, <quic_gokulsri@...cinc.com>,
<quic_sjaganat@...cinc.com>, <quic_kathirav@...cinc.com>,
<quic_arajkuma@...cinc.com>, <quic_anusha@...cinc.com>,
<quic_poovendh@...cinc.com>
Subject: Re: [PATCH V7 2/7] clk: qcom: Add Global Clock Controller driver for
IPQ9574
Thanks for taking time to review the patch!
On 2/6/2023 7:37 PM, Dmitry Baryshkov wrote:
> On 06/02/2023 12:33, Devi Priya wrote:
>> Add Global Clock Controller (GCC) driver for ipq9574 based devices
>>
>> Co-developed-by: Anusha Rao <quic_anusha@...cinc.com>
>> Signed-off-by: Anusha Rao <quic_anusha@...cinc.com>
>> Signed-off-by: Devi Priya <quic_devipriy@...cinc.com>
>> ---
>> Changes in V7:
>> - Used qcom_cc_probe instead of qcom_cc_really_probe in
>> gcc_ipq9574_probe
>>
>> drivers/clk/qcom/Kconfig | 8 +
>> drivers/clk/qcom/Makefile | 1 +
>> drivers/clk/qcom/gcc-ipq9574.c | 4295 ++++++++++++++++++++++++++++++++
>> 3 files changed, 4304 insertions(+)
>> create mode 100644 drivers/clk/qcom/gcc-ipq9574.c
>>
>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
>> index 5ab4b7dfe3c2..a9f01d67a500 100644
>> --- a/drivers/clk/qcom/Kconfig
>> +++ b/drivers/clk/qcom/Kconfig
>> @@ -173,6 +173,14 @@ config IPQ_GCC_8074
>> i2c, USB, SD/eMMC, etc. Select this for the root clock
>> of ipq8074.
>> +config IPQ_GCC_9574
>> + tristate "IPQ9574 Global Clock Controller"
>> + help
>> + Support for global clock controller on ipq9574 devices.
>> + Say Y if you want to use peripheral devices such as UART, SPI,
>> + i2c, USB, SD/eMMC, etc. Select this for the root clock
>> + of ipq9574.
>> +
>> config MSM_GCC_8660
>> tristate "MSM8660 Global Clock Controller"
>> help
>> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
>> index 3194465dd02c..51e6e5eb187b 100644
>> --- a/drivers/clk/qcom/Makefile
>> +++ b/drivers/clk/qcom/Makefile
>> @@ -27,6 +27,7 @@ obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
>> obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
>> obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
>> obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
>> +obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
>> obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
>> obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o
>> obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
>> diff --git a/drivers/clk/qcom/gcc-ipq9574.c
>> b/drivers/clk/qcom/gcc-ipq9574.c
>> new file mode 100644
>> index 000000000000..718106a9ac7b
>> --- /dev/null
>> +++ b/drivers/clk/qcom/gcc-ipq9574.c
>
> [skipped]
>
>> +static struct clk_branch gcc_snoc_pcie3_2lane_s_clk = {
>> + .halt_reg = 0x2e054,
>> + .clkr = {
>> + .enable_reg = 0x2e054,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data) {
>> + .name = "gcc_snoc_pcie3_2lane_s_clk",
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &pcie3_axi_s_clk_src.clkr.hw
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_regmap_mux pcie0_pipe_clk_src = {
>> + .reg = 0x28064,
>> + .shift = 8,
>> + .width = 2,
>> + .parent_map = gcc_pcie30_phy0_pipe_clk_xo_map,
>> + .clkr = {
>> + .hw.init = &(struct clk_init_data) {
>> + .name = "pcie0_pipe_clk_src",
>> + .parent_data = gcc_pcie30_phy0_pipe_clk_xo,
>> + .num_parents = ARRAY_SIZE(gcc_pcie30_phy0_pipe_clk_xo),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_regmap_mux_closest_ops,
>
>
> clk_regmap_phy_mux_ops ?
Okay, will update the ops and struct accordingly in the next series
>
>> + },
>> + },
>> +};
>> +
>> +static struct clk_regmap_mux pcie1_pipe_clk_src = {
>> + .reg = 0x29064,
>> + .shift = 8,
>> + .width = 2,
>> + .parent_map = gcc_pcie30_phy1_pipe_clk_xo_map,
>> + .clkr = {
>> + .hw.init = &(struct clk_init_data) {
>> + .name = "pcie1_pipe_clk_src",
>> + .parent_data = gcc_pcie30_phy1_pipe_clk_xo,
>> + .num_parents = ARRAY_SIZE(gcc_pcie30_phy1_pipe_clk_xo),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_regmap_mux_closest_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_regmap_mux pcie2_pipe_clk_src = {
>> + .reg = 0x2a064,
>> + .shift = 8,
>> + .width = 2,
>> + .parent_map = gcc_pcie30_phy2_pipe_clk_xo_map,
>> + .clkr = {
>> + .hw.init = &(struct clk_init_data) {
>> + .name = "pcie2_pipe_clk_src",
>> + .parent_data = gcc_pcie30_phy2_pipe_clk_xo,
>> + .num_parents = ARRAY_SIZE(gcc_pcie30_phy2_pipe_clk_xo),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_regmap_mux_closest_ops,
>
> clk_regmap_phy_mux_ops ?
Okay
>
>
>> + },
>> + },
>> +};
>> +
>> +static struct clk_regmap_mux pcie3_pipe_clk_src = {
>> + .reg = 0x2b064,
>> + .shift = 8,
>> + .width = 2,
>> + .parent_map = gcc_pcie30_phy3_pipe_clk_xo_map,
>> + .clkr = {
>> + .hw.init = &(struct clk_init_data) {
>> + .name = "pcie3_pipe_clk_src",
>> + .parent_data = gcc_pcie30_phy3_pipe_clk_xo,
>> + .num_parents = ARRAY_SIZE(gcc_pcie30_phy3_pipe_clk_xo),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_regmap_mux_closest_ops,
>
> clk_regmap_phy_mux_ops ?
Okay
>
>> + },
>> + },
>> +};
>
Best Regards,
Devi Priya
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