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Message-ID: <Y+PRGjn8a26pe5Dy@spud>
Date: Wed, 8 Feb 2023 16:43:06 +0000
From: Conor Dooley <conor@...nel.org>
To: Trevor Woerner <twoerner@...il.com>
Cc: linux-kernel@...r.kernel.org, Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Chen-Yu Tsai <wens@...e.org>,
Jernej Skrabec <jernej.skrabec@...il.com>,
Samuel Holland <samuel@...lland.org>,
linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-sunxi@...ts.linux.dev
Subject: Re: [PATCH] riscv: dts: nezha-d1: add gpio-line-names
Hey Trevor,
On Tue, Feb 07, 2023 at 08:45:03PM -0500, Trevor Woerner wrote:
> Add descriptive names so users can associate specific lines with their
> respective pins on the 40-pin header according to the schematics found at:
>
> http://dl.linux-sunxi.org/D1/D1_Nezha_development_board_schematic_diagram_20210224.pdf
Dunno about the sunxi folk, but ideally that'd be a Link: tag IMO.
>
> Signed-off-by: Trevor Woerner <twoerner@...il.com>
> ---
> .../boot/dts/allwinner/sun20i-d1-nezha.dts | 53 +++++++++++++++++++
> 1 file changed, 53 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
> index a0769185be97..33489c7619cb 100644
> --- a/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
> +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
> @@ -90,6 +90,15 @@ pcf8574a: gpio@38 {
> gpio-controller;
> #gpio-cells = <2>;
> #interrupt-cells = <2>;
> + gpio-line-names =
> + "pin13 [PP0,gpio8] ",
> + "pin16 [PP1,gpio10]",
> + "pin18 [PP2,gpio11]",
> + "pin26 [PP3,gpio17]",
> + "pin22 [PP4,gpio14]",
> + "pin28 [PP5,gpio19]",
> + "pin37 [PP6,gpio23]",
> + "pin11 [PP7,gpio6] ";
dtbs_check does not like this:
arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dtb: gpio@38: 'gpio-line-names' does not match any of the regexes: '^(.+-hog(-[0-9]+)?)$', 'pinctrl-[0-9]+'
From schema: Documentation/devicetree/bindings/gpio/nxp,pcf8575.yaml
> };
> };
>
> @@ -164,3 +173,47 @@ &usbphy {
> usb1_vbus-supply = <®_vcc>;
> status = "okay";
> };
> +
> +&pio {
> + gpio-line-names =
> + /* Port A */
> + "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "",
> + /* Port B */
> + "pin5 [PB0, gpio2/twi2-sck]",
> + "pin3 [PB1, gpio1/twi2-sda]",
> + "",
> + "pin38 [PB3, gpio24/i2s2-din]",
> + "pin40 [PB4, gpio25/i2s2-dout]",
> + "pin12 [PB5, gpio7/i2s-clk]",
> + "pin35 [PB6, gpio22/i2s2-lrck]",
> + "",
> + "pin8 [PB8, gpio4/uart0-txd]",
> + "pin10 [PB9, gpio5/uart0-rxd]",
> + "",
> + "",
> + "pin15 [PB12,gpio9]",
Why not pick a consistent styling w.r.t. the space between PB#, & gpio?
Cheers,
Conor.
> + "", "", "", "",
> + "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "",
> + /* Port C */
> + "",
> + "pin31 [PC1, gpio21]",
> + "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "",
> + /* Port D */
> + "", "", "", "", "", "", "", "",
> + "", "",
> + "pin24 [PD10,gpio16/spi1-ce0]",
> + "pin23 [PD11,gpio15/spi1-clk]",
> + "pin19 [PD12,gpio12/spi1-mosi]",
> + "pin21 [PD13,gpio13/spi1-miso]",
> + "pin27 [PD14,gpio18/spi1-hold]",
> + "pin29 [PD15,gpio20/spi1-wp]",
> + "", "", "", "", "", "",
> + "pin7 [PD22,gpio3/pwm]";
> +};
> --
> 2.36.0.rc2.17.g4027e30c53
>
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