lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Date:   Thu, 9 Feb 2023 15:54:35 +0000
From:   Robin Murphy <robin.murphy@....com>
To:     Evgenii Shatokhin <e.shatokhin@...ro.com>,
        Serge Semin <fancer.lancer@...il.com>
Cc:     Serge Semin <Sergey.Semin@...kalelectronics.ru>,
        kernel-team@...roid.com, Vidya Sagar <vidyas@...dia.com>,
        Christoph Hellwig <hch@...radead.org>,
        linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org,
        Gustavo Pimentel <gustavo.pimentel@...opsys.com>,
        Jingoo Han <jingoohan1@...il.com>,
        Rob Herring <robh@...nel.org>,
        Krzysztof WilczyƄski <kw@...ux.com>,
        Bjorn Helgaas <bhelgaas@...gle.com>, linux@...ro.com,
        Lorenzo Pieralisi <lpieralisi@...nel.org>,
        Will McVicker <willmcvicker@...gle.com>
Subject: Re: [PATCH v6 0/2] PCI: dwc: Add support for 64-bit MSI target
 addresses

On 2023-02-09 08:03, Evgenii Shatokhin wrote:
[...]
>> Currently the kernel PCIe subsystem doesn't provide a way to reserve a
>> range within the PCIe bus memory with no physical RAM behind and left
>> unused during the BARs resource initialization. Implementing such
>> functionality (perhaps in the framework of the P2P module or based on
>> it) would give the generic solution.
>>
>>>
>>> For now, we are probably better off with SoC-specific patches, when 
>>> we know
>>> which PCIe devices can possibly be used and what their restrictions are.
>>
>> Since you know that there is no any RAM below 4GB and you have
>> matching CPU and PCIe address spaces, then you can just take any
>> address below 4GB and use it to initialize the MSI-target address
>> (dw_pcie_rp.msi_data). But make sure that the peripheral PCIe-devices
>> don't use it for something application-specific (like accessing CPU
>> MMIO devices mapped to that base address). That seems like the most
>> universal solution for your case.
> 
> Interesting idea!
> Thank you, Sergey.

Yes, if the platform-specific driver knows enough to be able to pick a 
suitable "safe" MSI address, then I think allowing it to pre-set 
pp.msi_data, and only falling back to the dma-mapping workaround 
otherwise, sounds reasonable.

Thanks,
Robin.

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ