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Message-ID: <0fc54210-8e94-5901-f02f-7a2b110e32ec@linaro.org>
Date:   Thu, 9 Feb 2023 09:27:20 +0100
From:   neil.armstrong@...aro.org
To:     Bhupesh Sharma <bhupesh.sharma@...aro.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
        Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
        Andy Gross <agross@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konrad.dybcio@...aro.org>,
        Vinod Koul <vkoul@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>
Cc:     linux-arm-msm@...r.kernel.org, dmaengine@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] dt-bindings: dma: qcom,bam-dma: add optional memory
 interconnect properties

On 09/02/2023 09:25, Bhupesh Sharma wrote:
> On 2/8/23 2:38 PM, neil.armstrong@...aro.org wrote:
>> On 08/02/2023 10:03, Krzysztof Kozlowski wrote:
>>> On 07/02/2023 16:27, Dmitry Baryshkov wrote:
>>>> On 07/02/2023 15:35, Neil Armstrong wrote:
>>>>> On 07/02/2023 11:32, Dmitry Baryshkov wrote:
>>>>>> On 07/02/2023 12:03, Neil Armstrong wrote:
>>>>>>> Recents SoCs like the SM8450 or SM8550 requires memory interconnect
>>>>>>> in order to have functional DMA.
>>>>>>>
>>>>>>> Signed-off-by: Neil Armstrong <neil.armstrong@...aro.org>
>>>>>>> ---
>>>>>>>    Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml | 6 ++++++
>>>>>>>    1 file changed, 6 insertions(+)
>>>>>>
>>>>>> I suspect this will not work without a change for a driver.
>>>>>>
>>>>>
>>>>> I had the impression single interconnect entries would be taken in account
>>>>> by the platform core, but it doesn't seem to be the case, anyway I can;t
>>>>> find
>>>>> any code doing that.
>>>>
>>>> Probably you mixed interconnects and power-domains here.
>>>>
>>>
>>> The driver change was submitted some time ago:
>>> https://lore.kernel.org/all/20210505213731.538612-10-bhupesh.sharma@linaro.org/
>>>
>>> There is already DTS user of it and we expect driver to be resubmitted
>>> at some point.
>>>
>>> What I don't really get is that crypto driver sets bandwidth for
>>> interconnects, not the BAM. Why BAM needs interconnect? Usually you do
>>> not need to initialize some middle paths. Getting the final interconnect
>>> path (e.g. crypto-memory) is enough, because it includes everything in
>>> between.
>>
>> Indeed the interconnect on BAM may be redundant since QCE sets the BW,
>> I'll investigate to understand if it's also necessary on BAM.
> 
> Since we are already doing this via QCE driver (since crypto block on qcom SoCs employs BAM DMA services) via [1], this change is not needed for sm8150, sm8250, sm8350 and subsequent qcom SoCs (available presently), so this patch can be dropped.

Ack, I'll push a patch to remove the interconnect properties from the BAM node in sm8550.

Neil

> 
> [1]. https://www.spinics.net/lists/linux-arm-msm/msg142957.html
> 
> Thanks,
> Bhupesh

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