linux-kernel - Re: [PATCH v3] coresight: tmc: Don't enable TMC when it's not ready.

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <77bd4509-bd8b-3bcc-e94a-7593505e27c0@arm.com>
Date:   Thu, 9 Feb 2023 10:31:28 +0000
From:   Suzuki K Poulose <suzuki.poulose@....com>
To:     Yabin Cui <yabinc@...gle.com>,
        Mathieu Poirier <mathieu.poirier@...aro.org>,
        Mike Leach <mike.leach@...aro.org>,
        Leo Yan <leo.yan@...aro.org>, James Clark <james.clark@....com>
Cc:     coresight@...ts.linaro.org, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3] coresight: tmc: Don't enable TMC when it's not ready.

On 09/02/2023 01:08, Yabin Cui wrote:
> Friendly ping?
> 
> On Thu, Feb 2, 2023 at 1:46 PM Yabin Cui <yabinc@...gle.com> wrote:
>>
>> If TMC ETR is enabled without being ready, in later use we may
>> see AXI bus errors caused by accessing invalid addresses.
>>
>> Signed-off-by: Yabin Cui <yabinc@...gle.com>
>> ---
>> V1 -> V2: Make change to all TMCs instead of just ETR
>> V2 -> V3: Handle etr enable failure in tmc_read_unprepare_etr

As I mentioned, v2 was queued. Please could you update your changes on 
top of the coresight next branch and resend the patch ?

Suzuki