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Message-ID: <20230210061713.6449-2-changhuang.liang@starfivetech.com>
Date: Thu, 9 Feb 2023 22:17:10 -0800
From: Changhuang Liang <changhuang.liang@...rfivetech.com>
To: Vinod Koul <vkoul@...nel.org>,
Kishon Vijay Abraham I <kishon@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Emil Renner Berthing <kernel@...il.dk>,
Conor Dooley <conor@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Philipp Zabel <p.zabel@...gutronix.de>
CC: Jack Zhu <jack.zhu@...rfivetech.com>,
Changhuang Liang <changhuang.liang@...rfivetech.com>,
<linux-phy@...ts.infradead.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-riscv@...ts.infradead.org>
Subject: [PATCH v1 1/4] riscv: dts: starfive: jh7110: Add aon syscon node
Add aon syscon node for the Starfive JH7110 SoC. It can be used by
other modules such as DPHY.
Signed-off-by: Changhuang Liang <changhuang.liang@...rfivetech.com>
---
arch/riscv/boot/dts/starfive/jh7110.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index cfbaff4ea64b..bce3e407ab60 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -251,6 +251,11 @@ soc {
#size-cells = <2>;
ranges;
+ aon_syscon: aon_syscon@...10000 {
+ compatible = "syscon";
+ reg = <0x0 0x17010000 0x0 0x1000>;
+ };
+
clint: clint@...0000 {
compatible = "starfive,jh7110-clint", "sifive,clint0";
reg = <0x0 0x2000000 0x0 0x10000>;
--
2.25.1
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