linux-kernel - Re: [PATCH v1 4/4] Revert "arm64: dts: mt8173: add mmsel clocks for 4K support"

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Date:   Fri, 10 Feb 2023 12:59:26 +0100
From:   AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@...labora.com>
To:     matthias.bgg@...nel.org, robh+dt@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, matthias.bgg@...il.com
Cc:     devicetree@...r.kernel.org, linux-mediatek@...ts.infradead.org,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v1 4/4] Revert "arm64: dts: mt8173: add mmsel clocks for
 4K support"

Il 09/02/23 17:03, matthias.bgg@...nel.org ha scritto:
> From: Matthias Brugger <matthias.bgg@...il.com>
> 
> This reverts commit fc6634ac0e5380aeb1063275a2e9a583d41b2306.
> 
> The mmsys is a clock provider but does not have any clocks connected to
> it. Therefore assigned-clock properties should be applied to the users of mmsys.
> 
> This fixes the DT schema check:
> mediatek/mt8173-elm.dtb: syscon@...00000: 'assigned-clock-rates', 'assigned-clocks' do not match any of the regexes: 'pinctrl-[0-9]+'
> 
> Signed-off-by: Matthias Brugger <matthias.bgg@...il.com>

About solving schema checks: agreed.

Since this is impacting on multiple subsystems (display, vdec, venc), can we
instead move this to the topckgen node?
I didn't check if that would trigger another schema check, but I remember
doing that on Qualcomm DTs a bit of time ago.

The alternative would be to copy that over more than 10 nodes, which would
be a bit ... ugly.

Cheers,
Angelo

> ---
> 
>   arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 --
>   1 file changed, 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> index c47d7d900f283..b753547e250fe 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> @@ -988,8 +988,6 @@ mmsys: syscon@...00000 {
>   			compatible = "mediatek,mt8173-mmsys", "syscon";
>   			reg = <0 0x14000000 0 0x1000>;
>   			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
> -			assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
> -			assigned-clock-rates = <400000000>;
>   			#clock-cells = <1>;
>   			#reset-cells = <1>;
>   			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,