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Message-ID: <771cba9d-6c88-b7fb-64a8-f560b1e19eba@linaro.org>
Date: Fri, 10 Feb 2023 15:04:09 +0100
From: Konrad Dybcio <konrad.dybcio@...aro.org>
To: Bjorn Andersson <quic_bjorande@...cinc.com>,
Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>
Cc: Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will@...nel.org>, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH 1/4] arm64: dts: qcom: sc8280xp: Add USB-C-related DP
blocks
On 8.02.2023 04:46, Bjorn Andersson wrote:
> From: Bjorn Andersson <bjorn.andersson@...aro.org>
>
> Add the two DisplayPort controllers that are attached to QMP phys for
> providing display output on USB Type-C.
>
> Signed-off-by: Bjorn Andersson <bjorn.andersson@...aro.org>
> Signed-off-by: Bjorn Andersson <quic_bjorande@...cinc.com>
> ---
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 170 ++++++++++++++++++++++++-
> 1 file changed, 166 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index dceb7eb3106b..fcd393444f47 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -3155,6 +3155,20 @@ ports {
> #address-cells = <1>;
> #size-cells = <0>;
>
> + port@0 {
> + reg = <0>;
Generally, there should be a newline between properties and child
nodes.
> + mdss0_intf0_out: endpoint {
> + remote-endpoint = <&mdss0_dp0_in>;
> + };
> + };
> +
> + port@4 {
> + reg = <4>;
> + mdss0_intf4_out: endpoint {
> + remote-endpoint = <&mdss0_dp1_in>;
> + };
> + };
> +
> port@5 {
> reg = <5>;
> mdss0_intf5_out: endpoint {
> @@ -3199,6 +3213,154 @@ opp-600000000 {
> };
> };
>
> + mdss0_dp0: displayport-controller@...0000 {
> + compatible = "qcom,sc8280xp-dp";
> + reg = <0 0xae90000 0 0x200>,
> + <0 0xae90200 0 0x200>,
> + <0 0xae90400 0 0x600>,
> + <0 0xae91000 0 0x400>,
> + <0 0xae91400 0 0x400>;
> + interrupt-parent = <&mdss0>;
> + interrupts = <12>;
> + clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>,
> + <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>,
> + <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
> + <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
> + clock-names = "core_iface", "core_aux",
> + "ctrl_link",
> + "ctrl_link_iface", "stream_pixel";
I overlooked this previously, but please turn this into a vertical list.
With these fixed:
Reviewed-by: Konrad Dybcio <konrad.dybcio@...aro.org>
Konrad
> +
> + assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
> + <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
> + assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
> + <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
> +
> + phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>;
> + phy-names = "dp";
> +
> + #sound-dai-cells = <0>;
> +
> + operating-points-v2 = <&mdss0_dp0_opp_table>;
> + power-domains = <&rpmhpd SC8280XP_CX>;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + mdss0_dp0_in: endpoint {
> + remote-endpoint = <&mdss0_intf0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + };
> + };
> +
> + mdss0_dp0_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-160000000 {
> + opp-hz = /bits/ 64 <160000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-270000000 {
> + opp-hz = /bits/ 64 <270000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-540000000 {
> + opp-hz = /bits/ 64 <540000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> +
> + opp-810000000 {
> + opp-hz = /bits/ 64 <810000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> + };
> + };
> +
> + mdss0_dp1: displayport-controller@...8000 {
> + compatible = "qcom,sc8280xp-dp";
> + reg = <0 0xae98000 0 0x200>,
> + <0 0xae98200 0 0x200>,
> + <0 0xae98400 0 0x600>,
> + <0 0xae99000 0 0x400>,
> + <0 0xae99400 0 0x400>;
> + interrupt-parent = <&mdss0>;
> + interrupts = <13>;
> + clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>,
> + <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>,
> + <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
> + <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
> + clock-names = "core_iface", "core_aux",
> + "ctrl_link",
> + "ctrl_link_iface", "stream_pixel";
> +
> + assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
> + <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
> + assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
> + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
> +
> + phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
> + phy-names = "dp";
> +
> + #sound-dai-cells = <0>;
> +
> + operating-points-v2 = <&mdss0_dp1_opp_table>;
> + power-domains = <&rpmhpd SC8280XP_CX>;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + mdss0_dp1_in: endpoint {
> + remote-endpoint = <&mdss0_intf4_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + };
> + };
> +
> + mdss0_dp1_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-160000000 {
> + opp-hz = /bits/ 64 <160000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-270000000 {
> + opp-hz = /bits/ 64 <270000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-540000000 {
> + opp-hz = /bits/ 64 <540000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> +
> + opp-810000000 {
> + opp-hz = /bits/ 64 <810000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> + };
> + };
> +
> mdss0_dp2: displayport-controller@...a000 {
> compatible = "qcom,sc8280xp-dp";
> reg = <0 0xae9a000 0 0x200>,
> @@ -3387,10 +3549,10 @@ dispcc0: clock-controller@...0000 {
> clocks = <&gcc GCC_DISP_AHB_CLK>,
> <&rpmhcc RPMH_CXO_CLK>,
> <&sleep_clk>,
> - <0>,
> - <0>,
> - <0>,
> - <0>,
> + <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
> + <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
> + <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
> + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
> <&mdss0_dp2_phy 0>,
> <&mdss0_dp2_phy 1>,
> <&mdss0_dp3_phy 0>,
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