linux-kernel - [tip: perf/core] x86/perf/zhaoxin: Add stepping check for ZXC

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Date:   Sat, 11 Feb 2023 10:38:22 -0000
From:   "tip-bot2 for silviazhao" <tip-bot2@...utronix.de>
To:     linux-tip-commits@...r.kernel.org
Cc:     Arjan <8vvbbqzo567a@...pam.xutrox.com>,
        Kevin Brace <kevinbrace@....com>,
        silviazhao <silviazhao-oc@...oxin.com>,
        "Peter Zijlstra (Intel)" <peterz@...radead.org>, x86@...nel.org,
        linux-kernel@...r.kernel.org
Subject: [tip: perf/core] x86/perf/zhaoxin: Add stepping check for ZXC

The following commit has been merged into the perf/core branch of tip:

Commit-ID:     fd636b6a9bc6034f2e5bb869658898a2b472c037
Gitweb:        https://git.kernel.org/tip/fd636b6a9bc6034f2e5bb869658898a2b472c037
Author:        silviazhao <silviazhao-oc@...oxin.com>
AuthorDate:    Wed, 08 Feb 2023 16:27:22 +08:00
Committer:     Peter Zijlstra <peterz@...radead.org>
CommitterDate: Sat, 11 Feb 2023 11:18:12 +01:00

x86/perf/zhaoxin: Add stepping check for ZXC

Some of Nano series processors will lead GP when accessing
PMC fixed counter. Meanwhile, their hardware support for PMC
has not announced externally. So exclude Nano CPUs from ZXC
by checking stepping information. This is an unambiguous way
to differentiate between ZXC and Nano CPUs.

Following are Nano and ZXC FMS information:
Nano FMS: Family=6, Model=F, Stepping=[0-A][C-D]
ZXC FMS:  Family=6, Model=F, Stepping=E-F OR
          Family=6, Model=0x19, Stepping=0-3

Fixes: 3a4ac121c2ca ("x86/perf: Add hardware performance events support for Zhaoxin CPU.")

Reported-by: Arjan <8vvbbqzo567a@...pam.xutrox.com>
Reported-by: Kevin Brace <kevinbrace@....com>
Signed-off-by: silviazhao <silviazhao-oc@...oxin.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@...radead.org>
Link: https://bugzilla.kernel.org/show_bug.cgi?id=212389
---
 arch/x86/events/zhaoxin/core.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/x86/events/zhaoxin/core.c b/arch/x86/events/zhaoxin/core.c
index 949d845..3e9acda 100644
--- a/arch/x86/events/zhaoxin/core.c
+++ b/arch/x86/events/zhaoxin/core.c
@@ -541,7 +541,13 @@ __init int zhaoxin_pmu_init(void)
 
 	switch (boot_cpu_data.x86) {
 	case 0x06:
-		if (boot_cpu_data.x86_model == 0x0f || boot_cpu_data.x86_model == 0x19) {
+		/*
+		 * Support Zhaoxin CPU from ZXC series, exclude Nano series through FMS.
+		 * Nano FMS: Family=6, Model=F, Stepping=[0-A][C-D]
+		 * ZXC FMS: Family=6, Model=F, Stepping=E-F OR Family=6, Model=0x19, Stepping=0-3
+		 */
+		if ((boot_cpu_data.x86_model == 0x0f && boot_cpu_data.x86_stepping >= 0x0e) ||
+			boot_cpu_data.x86_model == 0x19) {
 
 			x86_pmu.max_period = x86_pmu.cntval_mask >> 1;