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Message-Id: <20230212205506.1992714-2-Mr.Bossman075@gmail.com>
Date: Sun, 12 Feb 2023 15:55:04 -0500
From: Jesse Taube <mr.bossman075@...il.com>
To: linux-riscv@...ts.infradead.org
Cc: linux-kernel@...r.kernel.org,
Jesse Taube <Mr.Bossman075@...il.com>,
Yimin Gu <ustcymgu@...il.com>,
Waldemar Brodkorb <wbx@...nadk.org>,
Albert Ou <aou@...s.berkeley.edu>,
Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Conor Dooley <conor.dooley@...rochip.com>,
kernel test robot <lkp@...el.com>
Subject: [PATCH v2 1/3] clk: k210: remove an implicit 64-bit division
From: Conor Dooley <conor.dooley@...rochip.com>
The K210 clock driver depends on SOC_CANAAN, which is only selectable
when !MMU on RISC-V. !MMU is not possible on 32-bit yet, but patches
have been sent for its enabling. The kernel test robot reported this
implicit 64-bit division there.
Replace the implicit division with an explicit one.
Reported-by: kernel test robot <lkp@...el.com>
Link: https://lore.kernel.org/linux-riscv/202301201538.zNlqgE4L-lkp@intel.com/
Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
Signed-off-by: Jesse Taube <Mr.Bossman075@...il.com>
---
drivers/clk/clk-k210.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/clk-k210.c b/drivers/clk/clk-k210.c
index 67a7cb3503c3..4eed667eddaf 100644
--- a/drivers/clk/clk-k210.c
+++ b/drivers/clk/clk-k210.c
@@ -495,7 +495,7 @@ static unsigned long k210_pll_get_rate(struct clk_hw *hw,
f = FIELD_GET(K210_PLL_CLKF, reg) + 1;
od = FIELD_GET(K210_PLL_CLKOD, reg) + 1;
- return (u64)parent_rate * f / (r * od);
+ return div_u64((u64)parent_rate * f, r * od);
}
static const struct clk_ops k210_pll_ops = {
--
2.39.0
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