linux-kernel - [tip: timers/core] dt-bindings: timer: Add bindings for the RISC-V timer device

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <167631278506.4906.15498041035078946448.tip-bot2@tip-bot2>
Date:   Mon, 13 Feb 2023 18:26:25 -0000
From:   "tip-bot2 for Anup Patel" <tip-bot2@...utronix.de>
To:     linux-tip-commits@...r.kernel.org
Cc:     Anup Patel <apatel@...tanamicro.com>,
        Conor Dooley <conor.dooley@...rochip.com>,
        Rob Herring <robh@...nel.org>,
        Palmer Dabbelt <palmer@...osinc.com>,
        Daniel Lezcano <daniel.lezcano@...nel.org>, x86@...nel.org,
        linux-kernel@...r.kernel.org
Subject: [tip: timers/core] dt-bindings: timer: Add bindings for the RISC-V
 timer device

The following commit has been merged into the timers/core branch of tip:

Commit-ID:     e2bcf2d876fd7ca6ecca09794ac58d7e3a544794
Gitweb:        https://git.kernel.org/tip/e2bcf2d876fd7ca6ecca09794ac58d7e3a544794
Author:        Anup Patel <apatel@...tanamicro.com>
AuthorDate:    Tue, 03 Jan 2023 19:41:01 +05:30
Committer:     Daniel Lezcano <daniel.lezcano@...aro.org>
CommitterDate: Mon, 13 Feb 2023 13:10:16 +01:00

dt-bindings: timer: Add bindings for the RISC-V timer device

We add DT bindings for a separate RISC-V timer DT node which can
be used to describe implementation specific behaviour (such as
timer interrupt not triggered during non-retentive suspend).

Signed-off-by: Anup Patel <apatel@...tanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>
Reviewed-by: Rob Herring <robh@...nel.org>
Acked-by: Palmer Dabbelt <palmer@...osinc.com>
Link: https://lore.kernel.org/r/20230103141102.772228-3-apatel@ventanamicro.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@...nel.org>
---
 Documentation/devicetree/bindings/timer/riscv,timer.yaml | 52 +++++++-
 1 file changed, 52 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/timer/riscv,timer.yaml

diff --git a/Documentation/devicetree/bindings/timer/riscv,timer.yaml b/Documentation/devicetree/bindings/timer/riscv,timer.yaml
new file mode 100644
index 0000000..38d67e1
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/riscv,timer.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/riscv,timer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RISC-V timer
+
+maintainers:
+  - Anup Patel <anup@...infault.org>
+
+description: |+
+  RISC-V platforms always have a RISC-V timer device for the supervisor-mode
+  based on the time CSR defined by the RISC-V privileged specification. The
+  timer interrupts of this device are configured using the RISC-V SBI Time
+  extension or the RISC-V Sstc extension.
+
+  The clock frequency of RISC-V timer device is specified via the
+  "timebase-frequency" DT property of "/cpus" DT node which is described
+  in Documentation/devicetree/bindings/riscv/cpus.yaml
+
+properties:
+  compatible:
+    enum:
+      - riscv,timer
+
+  interrupts-extended:
+    minItems: 1
+    maxItems: 4096   # Should be enough?
+
+  riscv,timer-cannot-wake-cpu:
+    type: boolean
+    description:
+      If present, the timer interrupt cannot wake up the CPU from one or
+      more suspend/idle states.
+
+additionalProperties: false
+
+required:
+  - compatible
+  - interrupts-extended
+
+examples:
+  - |
+    timer {
+      compatible = "riscv,timer";
+      interrupts-extended = <&cpu1intc 5>,
+                            <&cpu2intc 5>,
+                            <&cpu3intc 5>,
+                            <&cpu4intc 5>;
+    };
+...