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Message-ID: <32a41b0f-48e2-a87b-9736-1e10fe8859d9@collabora.com>
Date: Mon, 13 Feb 2023 15:59:26 +0100
From: AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>
To: Tinghan Shen <tinghan.shen@...iatek.com>,
Bjorn Andersson <andersson@...nel.org>,
Mathieu Poirier <mathieu.poirier@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Matthias Brugger <matthias.bgg@...il.com>
Cc: linux-remoteproc@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org,
Project_Global_Chrome_Upstream_Group@...iatek.com
Subject: Re: [PATCH v6 09/12] remoteproc: mediatek: Setup MT8195 SCP core 1
SRAM offset
Il 13/02/23 04:37, Tinghan Shen ha scritto:
> Because MT8195 SCP core 0 and core 1 both boot from head of SRAM and
> have the same viewpoint of SRAM, SCP has a "core 1 SRAM offset"
> configuration to control the access destination of SCP core 1 to boot
> core 1 from different SRAM location.
>
> The "core 1 SRAM offset" configuration is composed by a range
> and an offset. It works like a simple memory mapped mechanism.
> When SCP core 1 accesses a SRAM address located in the range,
> the SCP bus adds the configured offset to the address to
> shift the physical destination address on SCP SRAM. This shifting is
> transparent to the software running on SCP core 1.
>
> Signed-off-by: Tinghan Shen <tinghan.shen@...iatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
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