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Message-ID: <20230214031114.926-9-yong.wu@mediatek.com>
Date: Tue, 14 Feb 2023 11:11:11 +0800
From: Yong Wu <yong.wu@...iatek.com>
To: Joerg Roedel <joro@...tes.org>,
Matthias Brugger <matthias.bgg@...il.com>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
Rob Herring <robh+dt@...nel.org>
CC: Will Deacon <will@...nel.org>, Robin Murphy <robin.murphy@....com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Hans Verkuil <hverkuil@...all.nl>, <nfraprado@...labora.com>,
<linux-media@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-mediatek@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, <iommu@...ts.linux.dev>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>,
<mingyuan.ma@...iatek.com>, <yf.wang@...iatek.com>,
<jianjiao.zeng@...iatek.com>,
Yunfei Dong <yunfei.dong@...iatek.com>,
kyrie wu <kyrie.wu@...iatek.corp-partner.google.com>,
<chengci.xu@...iatek.com>, <youlin.pei@...iatek.com>,
<anan.sun@...iatek.com>, Yong Wu <yong.wu@...iatek.com>
Subject: [PATCH v3 08/11] iommu/mediatek: Add a gap for the iova regions
As the removed property in the vcodec dt-binding, the property is:
dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
The length is 0xfff0_0000 rather than 0x1_0000_0000, this means it
requires 1M as a gap. This is because the end address for some vcodec
HW is (address + size). If the size is 4G, the end address may be
0x2_0000_0000, and the width for vcodec register only is 32, then the
HW may get the ZERO address.
Currently the consumer's dma-ranges property doesn't work, IOMMU
has to consider this case. Add a bigger gap(8M) for all the regions
to avoid it.
Signed-off-by: Yong Wu <yong.wu@...iatek.com>
---
drivers/iommu/mtk_iommu.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 995e59cabf6c..4503fba72384 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -329,7 +329,7 @@ static LIST_HEAD(m4ulist); /* List all the M4U HWs */
#define for_each_m4u(data, head) list_for_each_entry(data, head, list)
static const struct mtk_iommu_iova_region single_domain[] = {
- {.iova_base = 0, .size = SZ_4G},
+ {.iova_base = 0, .size = SZ_4G - SZ_8M},
};
#define MT8192_MULTI_REGION_MAX_NR 6
@@ -338,11 +338,11 @@ static const struct mtk_iommu_iova_region single_domain[] = {
MT8192_MULTI_REGION_MAX_NR : 1)
static const struct mtk_iommu_iova_region mt8192_multi_dom[MT8192_MULTI_REGION_NR] = {
- { .iova_base = 0x0, .size = SZ_4G}, /* 0 ~ 4G */
+ { .iova_base = 0x0, .size = SZ_4G - SZ_8M}, /* 0 ~ 4G, 8M as a gap. */
#if IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)
- { .iova_base = SZ_4G, .size = SZ_4G}, /* 4G ~ 8G */
- { .iova_base = SZ_4G * 2, .size = SZ_4G}, /* 8G ~ 12G */
- { .iova_base = SZ_4G * 3, .size = SZ_4G}, /* 12G ~ 16G */
+ { .iova_base = SZ_4G, .size = SZ_4G - SZ_8M}, /* 4G ~ 8G */
+ { .iova_base = SZ_4G * 2, .size = SZ_4G - SZ_8M}, /* 8G ~ 12G */
+ { .iova_base = SZ_4G * 3, .size = SZ_4G - SZ_8M}, /* 12G ~ 16G */
{ .iova_base = 0x240000000ULL, .size = 0x4000000}, /* CCU0 */
{ .iova_base = 0x244000000ULL, .size = 0x4000000}, /* CCU1 */
--
2.18.0
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