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Message-ID: <a0a2afa5-e364-b7af-958f-3d4a34672337@opensource.wdc.com>
Date: Wed, 15 Feb 2023 10:03:56 +0900
From: Damien Le Moal <damien.lemoal@...nsource.wdc.com>
To: Rick Wertenbroek <rick.wertenbroek@...il.com>,
alberto.dassatti@...g-vd.ch
Cc: xxm@...k-chips.com, rick.wertenbroek@...g-vd.ch,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Heiko Stuebner <heiko@...ech.de>,
Shawn Lin <shawn.lin@...k-chips.com>,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
Krzysztof WilczyĆski <kw@...ux.com>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Jani Nikula <jani.nikula@...el.com>,
Rodrigo Vivi <rodrigo.vivi@...el.com>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Mikko Kovanen <mikko.kovanen@...amobile.com>,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-pci@...r.kernel.org
Subject: Re: [PATCH v2 5/9] arm64: dts: rockchip: Add dtsi entry for RK3399
PCIe endpoint core
On 2/14/23 23:08, Rick Wertenbroek wrote:
> Add dtsi entry for RK3399 PCIe endpoint core in the device tree.
> The status is "disabled" by default, so it will not be loaded unless
> explicitly chosen to. The RK3399 PCIe endpoit core should be enabled
> with the RK3399 PCIe root complex disabled because the RK3399 PCIe
> controller can only work one mode at the time, either in "root complex"
> mode or in "endpoint" mode.
>
> Signed-off-by: Rick Wertenbroek <rick.wertenbroek@...il.com>
You should also update the file:
Documentation/devicetree/bindings/pci/rockchip-pcie-ep.txt
The example there is broken...
Otherwise, this works great for me.
--
Damien Le Moal
Western Digital Research
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