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Message-ID: <206a3629-f0be-da63-d2dd-7f2dd366eb08@starfivetech.com>
Date: Wed, 15 Feb 2023 20:26:01 +0800
From: William Qiu <william.qiu@...rfivetech.com>
To: Emil Renner Berthing <emil.renner.berthing@...onical.com>
CC: <linux-riscv@...ts.infradead.org>, <devicetree@...r.kernel.org>,
<linux-mmc@...r.kernel.org>, Rob Herring <robh+dt@...nel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@...aro.org>,
Jaehoon Chung <jh80.chung@...sung.com>,
Ulf Hansson <ulf.hansson@...aro.org>,
<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v4 3/4] riscv: dts: starfive: Add mmc node
On 2023/2/15 20:12, Emil Renner Berthing wrote:
> On Wed, 15 Feb 2023 at 12:35, William Qiu <william.qiu@...rfivetech.com> wrote:
>>
>> Add the mmc node for the StarFive JH7110 SoC.
>> Set mmco node to emmc and set mmc1 node to sd.
>>
>> Signed-off-by: William Qiu <william.qiu@...rfivetech.com>
>> ---
>> .../jh7110-starfive-visionfive-2.dtsi | 23 +++++++++
>> arch/riscv/boot/dts/starfive/jh7110.dtsi | 47 +++++++++++++++++++
>> 2 files changed, 70 insertions(+)
>>
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> index c60280b89c73..e1a0248e907f 100644
>> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> @@ -42,6 +42,29 @@ &rtc_osc {
>> clock-frequency = <32768>;
>> };
>>
>> +&mmc0 {
>> + max-frequency = <100000000>;
>> + bus-width = <8>;
>> + cap-mmc-highspeed;
>> + mmc-ddr-1_8v;
>> + mmc-hs200-1_8v;
>> + non-removable;
>> + cap-mmc-hw-reset;
>> + post-power-on-delay-ms = <200>;
>> + status = "okay";
>> +};
>> +
>> +&mmc1 {
>> + max-frequency = <100000000>;
>> + bus-width = <4>;
>> + no-sdio;
>> + no-mmc;
>> + broken-cd;
>> + cap-sd-highspeed;
>> + post-power-on-delay-ms = <200>;
>> + status = "okay";
>> +};
>> +
>> &gmac0_rmii_refin {
>> clock-frequency = <50000000>;
>> };
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> index 64d260ea1f29..17f7b3ee6ca3 100644
>> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> @@ -314,6 +314,11 @@ uart2: serial@...20000 {
>> status = "disabled";
>> };
>>
>> + stg_syscon: syscon@...40000 {
>> + compatible = "starfive,jh7110-stg-syscon", "syscon";
>> + reg = <0x0 0x10240000 0x0 0x1000>;
>> + };
>> +
>> uart3: serial@...00000 {
>> compatible = "snps,dw-apb-uart";
>> reg = <0x0 0x12000000 0x0 0x10000>;
>> @@ -370,6 +375,11 @@ syscrg: clock-controller@...20000 {
>> #reset-cells = <1>;
>> };
>>
>> + sys_syscon: syscon@...30000 {
>> + compatible = "starfive,jh7110-sys-syscon", "syscon";
>> + reg = <0x0 0x13030000 0x0 0x1000>;
>> + };
>> +
>> gpio: gpio@...40000 {
>> compatible = "starfive,jh7110-sys-pinctrl";
>> reg = <0x0 0x13040000 0x0 0x10000>;
>> @@ -397,6 +407,11 @@ aoncrg: clock-controller@...00000 {
>> #reset-cells = <1>;
>> };
>>
>> + aon_syscon: syscon@...10000 {
>> + compatible = "starfive,jh7110-aon-syscon", "syscon";
>> + reg = <0x0 0x17010000 0x0 0x1000>;
>> + };
>> +
>> gpioa: gpio@...20000 {
>> compatible = "starfive,jh7110-aon-pinctrl";
>> reg = <0x0 0x17020000 0x0 0x10000>;
>> @@ -407,5 +422,37 @@ gpioa: gpio@...20000 {
>> gpio-controller;
>> #gpio-cells = <2>;
>> };
>> +
>> + mmc0: mmc@...10000 {
>> + compatible = "starfive,jh7110-mmc";
>> + reg = <0x0 0x16010000 0x0 0x10000>;
>> + clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>,
>> + <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
>> + clock-names = "biu","ciu";
>> + resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>;
>> + reset-names = "reset";
>> + interrupts = <74>;
>> + fifo-depth = <32>;
>> + fifo-watermark-aligned;
>> + data-addr = <0>;
>> + starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
>> + status = "disabled";
>> + };
>> +
>> + mmc1: mmc@...20000 {
>> + compatible = "starfive,jh7110-mmc";
>> + reg = <0x0 0x16020000 0x0 0x10000>;
>> + clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>,
>> + <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
>> + clock-names = "biu","ciu";
>> + resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>;
>> + reset-names = "reset";
>> + interrupts = <75>;
>> + fifo-depth = <32>;
>> + fifo-watermark-aligned;
>> + data-addr = <0>;
>> + starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>;
>> + status = "disabled";
>> + };
>
> Hi William,
>
> These nodes still don't seem to be sorted by address, eg. by the
> number after the @
> Also please move the dt-binding patch before this one, so dtb_check
> won't fail no matter where git bisect happens to land.
>
> /Emil
>
Hi Emil,
I'll update it in next version.
Best Regards
William
>> };
>> };
>> --
>> 2.34.1
>>
>>
>> _______________________________________________
>> linux-riscv mailing list
>> linux-riscv@...ts.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-riscv
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