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Message-ID: <202302160113.Sfcg9tC9-lkp@intel.com>
Date: Thu, 16 Feb 2023 01:24:12 +0800
From: kernel test robot <lkp@...el.com>
To: Florian Fainelli <f.fainelli@...il.com>,
linux-arm-kernel@...ts.infradead.org
Cc: oe-kbuild-all@...ts.linux.dev,
Florian Fainelli <f.fainelli@...il.com>,
Thomas Gleixner <tglx@...utronix.de>,
Marc Zyngier <maz@...nel.org>,
Oliver Upton <oliver.upton@...ux.dev>,
linux-kernel@...r.kernel.org, Sudeep Holla <sudeep.holla@....com>,
Broadcom internal kernel review list
<bcm-kernel-feedback-list@...adcom.com>
Subject: Re: [PATCH 2/3] irqchip/gic-v3: Propagate gic_cpu_pm_init() return
code
Hi Florian,
I love your patch! Yet something to improve:
[auto build test ERROR on tip/irq/core]
[also build test ERROR on soc/for-next linus/master v6.2-rc8 next-20230215]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Florian-Fainelli/irqchip-gic-v3-Use-switch-case-statements-in-gic_cpu_pm_notifier/20230215-073628
patch link: https://lore.kernel.org/r/20230214233426.2994501-3-f.fainelli%40gmail.com
patch subject: [PATCH 2/3] irqchip/gic-v3: Propagate gic_cpu_pm_init() return code
config: arm64-randconfig-r011-20230213 (https://download.01.org/0day-ci/archive/20230216/202302160113.Sfcg9tC9-lkp@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/8657e4fd7d9714934c7660bc3693d9ad507679a0
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Florian-Fainelli/irqchip-gic-v3-Use-switch-case-statements-in-gic_cpu_pm_notifier/20230215-073628
git checkout 8657e4fd7d9714934c7660bc3693d9ad507679a0
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm64 olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash drivers/irqchip/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@...el.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202302160113.Sfcg9tC9-lkp@intel.com/
All errors (new ones prefixed by >>):
drivers/irqchip/irq-gic-v3.c: In function 'gic_init_bases':
>> drivers/irqchip/irq-gic-v3.c:1896:13: error: void value not ignored as it ought to be
1896 | err = gic_cpu_pm_init();
| ^
vim +1896 drivers/irqchip/irq-gic-v3.c
1825
1826 static int __init gic_init_bases(void __iomem *dist_base,
1827 struct redist_region *rdist_regs,
1828 u32 nr_redist_regions,
1829 u64 redist_stride,
1830 struct fwnode_handle *handle)
1831 {
1832 u32 typer;
1833 int err;
1834
1835 if (!is_hyp_mode_available())
1836 static_branch_disable(&supports_deactivate_key);
1837
1838 if (static_branch_likely(&supports_deactivate_key))
1839 pr_info("GIC: Using split EOI/Deactivate mode\n");
1840
1841 gic_data.fwnode = handle;
1842 gic_data.dist_base = dist_base;
1843 gic_data.redist_regions = rdist_regs;
1844 gic_data.nr_redist_regions = nr_redist_regions;
1845 gic_data.redist_stride = redist_stride;
1846
1847 /*
1848 * Find out how many interrupts are supported.
1849 */
1850 typer = readl_relaxed(gic_data.dist_base + GICD_TYPER);
1851 gic_data.rdists.gicd_typer = typer;
1852
1853 gic_enable_quirks(readl_relaxed(gic_data.dist_base + GICD_IIDR),
1854 gic_quirks, &gic_data);
1855
1856 pr_info("%d SPIs implemented\n", GIC_LINE_NR - 32);
1857 pr_info("%d Extended SPIs implemented\n", GIC_ESPI_NR);
1858
1859 /*
1860 * ThunderX1 explodes on reading GICD_TYPER2, in violation of the
1861 * architecture spec (which says that reserved registers are RES0).
1862 */
1863 if (!(gic_data.flags & FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539))
1864 gic_data.rdists.gicd_typer2 = readl_relaxed(gic_data.dist_base + GICD_TYPER2);
1865
1866 gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops,
1867 &gic_data);
1868 gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist));
1869 gic_data.rdists.has_rvpeid = true;
1870 gic_data.rdists.has_vlpis = true;
1871 gic_data.rdists.has_direct_lpi = true;
1872 gic_data.rdists.has_vpend_valid_dirty = true;
1873
1874 if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) {
1875 err = -ENOMEM;
1876 goto out_free;
1877 }
1878
1879 irq_domain_update_bus_token(gic_data.domain, DOMAIN_BUS_WIRED);
1880
1881 gic_data.has_rss = !!(typer & GICD_TYPER_RSS);
1882
1883 if (typer & GICD_TYPER_MBIS) {
1884 err = mbi_init(handle, gic_data.domain);
1885 if (err)
1886 pr_err("Failed to initialize MBIs\n");
1887 }
1888
1889 set_handle_irq(gic_handle_irq);
1890
1891 gic_update_rdist_properties();
1892
1893 gic_dist_init();
1894 gic_cpu_init();
1895 gic_smp_init();
> 1896 err = gic_cpu_pm_init();
1897 if (err)
1898 goto out_set_handle;
1899
1900 if (gic_dist_supports_lpis()) {
1901 its_init(handle, &gic_data.rdists, gic_data.domain);
1902 its_cpu_init();
1903 its_lpi_memreserve_init();
1904 } else {
1905 if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1906 gicv2m_init(handle, gic_data.domain);
1907 }
1908
1909 gic_enable_nmi_support();
1910
1911 return 0;
1912
1913 out_set_handle:
1914 set_handle_irq(NULL);
1915 out_free:
1916 if (gic_data.domain)
1917 irq_domain_remove(gic_data.domain);
1918 free_percpu(gic_data.rdists.rdist);
1919 return err;
1920 }
1921
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests
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