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Message-Id: <20230216175347.99778-2-prabhakar.mahadev-lad.rj@bp.renesas.com>
Date: Thu, 16 Feb 2023 17:53:45 +0000
From: Prabhakar <prabhakar.csengg@...il.com>
To: Geert Uytterhoeven <geert+renesas@...der.be>,
Magnus Damm <magnus.damm@...il.com>
Cc: Laurent Pinchart <laurent.pinchart+renesas@...asonboard.com>,
Niklas Söderlund
<niklas.soderlund+renesas@...natech.se>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
linux-renesas-soc@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Prabhakar <prabhakar.csengg@...il.com>,
Biju Das <biju.das.jz@...renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: [PATCH 1/3] arm64: dts: renesas: r9a07g044: Add CSI and CRU nodes
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Add CSI and CRU nodes r9a07g044 (RZ/G2L) SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 79 ++++++++++++++++++++++
1 file changed, 79 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 9a3e18abae39..68bd70210d08 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -627,6 +627,85 @@ sbc: spi@...60000 {
status = "disabled";
};
+ cru: video@...30000 {
+ compatible = "renesas,r9a07g044-cru", "renesas,rzg2l-cru";
+ reg = <0 0x10830000 0 0x400>;
+ clocks = <&cpg CPG_MOD SOC_PREFIX(CRU_VCLK)>,
+ <&cpg CPG_MOD SOC_PREFIX(CRU_PCLK)>,
+ <&cpg CPG_MOD SOC_PREFIX(CRU_ACLK)>;
+ clock-names = "video", "apb", "axi";
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "image_conv", "image_conv_err", "axi_mst_err";
+ resets = <&cpg SOC_PREFIX(CRU_PRESETN)>,
+ <&cpg SOC_PREFIX(CRU_ARESETN)>;
+ reset-names = "presetn", "aresetn";
+ power-domains = <&cpg>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <0>;
+ cruparallel: endpoint@0 {
+ reg = <0>;
+ };
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+ crucsi2: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&csi2cru>;
+ };
+ };
+ };
+ };
+
+ csi2: csi2@...30400 {
+ compatible = "renesas,r9a07g044-csi2", "renesas,rzg2l-csi2";
+ reg = <0 0x10830400 0 0xfc00>;
+ interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD SOC_PREFIX(CRU_SYSCLK)>,
+ <&cpg CPG_MOD SOC_PREFIX(CRU_VCLK)>,
+ <&cpg CPG_MOD SOC_PREFIX(CRU_PCLK)>;
+ clock-names = "system", "video", "apb";
+ resets = <&cpg SOC_PREFIX(CRU_PRESETN)>,
+ <&cpg SOC_PREFIX(CRU_CMN_RSTB)>;
+ reset-names = "presetn", "cmn-rstb";
+ power-domains = <&cpg>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ csi2cru: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&crucsi2>;
+ };
+ };
+ };
+ };
+
cpg: clock-controller@...10000 {
compatible = "renesas,r9a07g044-cpg";
reg = <0 0x11010000 0 0x10000>;
--
2.25.1
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