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Message-ID: <20230216053322.11596-1-yong.wu@mediatek.com>
Date: Thu, 16 Feb 2023 13:33:16 +0800
From: Yong Wu <yong.wu@...iatek.com>
To: Joerg Roedel <joro@...tes.org>, Will Deacon <will@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>
CC: Robin Murphy <robin.murphy@....com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Yong Wu <yong.wu@...iatek.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>, <iommu@...ts.linux.dev>,
<linux-mediatek@...ts.infradead.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>, <mingyuan.ma@...iatek.com>,
<yf.wang@...iatek.com>, <jianjiao.zeng@...iatek.com>,
<chengci.xu@...iatek.com>, <youlin.pei@...iatek.com>
Subject: [PATCH v7 0/6] MT8188 IOMMU SUPPORT
MT8188 have 3 IOMMU HWs. 2 IOMMU HW is for multimedia, and 1 IOMMU HW
is for infra-master, like PCIe.
About the 2 MM IOMMU HW, the connection could be something like this:
IOMMU(VDO) IOMMU(VPP)
| |
SMI_COMMON(VDO) SMI_COMMON(VPP)
--------------- ----------------
| | ... | | ...
larb0 larb2 ... larb1 larb3 ...
INFRA IOMMU does not have SMI, the master connects to IOMMU directly.
Although multiple banks supported in MT8188, we only use one of them,
which means PCIe is put in bank0 of INFRA IOMMU.
So we have two pgtable for MT8188, specifically, these two MM IOMMU HW
share a pgtable while INFRA IOMMU HW use a independent pgtable.
Another change is that we add some SMC command for INFRA master to
enable/disable INFRA IOMMU in ATF considering security concerns.
We also adjust the flow of mtk_iommu_config to reduce indention.
changes since v7:
- Base on mtk-iommu-dma-range-v4:
https://lore.kernel.org/linux-mediatek/20230215062544.8677-1-yong.wu@mediatek.com/
- Add a new patch for two IOMMU share pagetable issue.
- Add a new patch for adding iova_region_larb_msk for mt8188.
- Add the comment in the dt-binding header file about larb index.
This is for readable when updating the iova_region_larb_msk.
Since there is something wrong for chengci's mail account when sending
to devicetree mail list, we don't know why. I help send this patchset.
https://lore.kernel.org/linux-mediatek/5a916595-12ee-92e6-d380-84146dd75218@linaro.org/
changes since v6:
https://lore.kernel.org/linux-mediatek/20221223101439.494-1-chengci.xu@mediatek.com/
- base on tag: next-20221220.
- update commit message of patch[2/4].
changes since v5:
- base on tag: next-20221205.
- add flag PGTABLE_PA_35_EN for all IOMMU in MT8188.
- modify the type of "portid_msk" from "u32" to "unsigned long".
changes since v4:
- base on tag: next-20221018.
- add patch[2/4] to reduce indention by adjust mtk_iommu_config flow.
changes since v3:
- base on tag: next-20220916.
- use license "GPL-2.0-only OR BSD-2-Clause" in bingings head file.
- drop redundant "portid" assignment when configure infra master.
- reduce indentation by using "else if" when config infra master.
- update probe flow about "pericfg" for CFG_IFA_MASTER_IN_ATF.
- drop unused "pericfg_comp_str" in mt8188_data_infra.
- drop words like "This commit/patch".
changes since v2:
- base on tag: next-20220831.
- rename "mt8188-memory-port.h" to "mediatek,mt8188-memory-port.h".
- use dual-license in "mediatek,mt8188-memory-port.h"
- remove unnecessary "()" when define SMI_LARB_ID
changes since v1:
- base on tag: next-20220803.
- adds MT8188 IOMMU support.
Chengci.Xu (5):
dt-bindings: mediatek: mt8188: Add binding for MM & INFRA IOMMU
iommu/mediatek: Fix two IOMMU share pagetable issue
iommu/mediatek: Adjust mtk_iommu_config flow
iommu/mediatek: Add enable IOMMU SMC command for INFRA master
iommu/mediatek: Add MT8188 IOMMU Support
Yong Wu (1):
iommu/mediatek: mt8188: Add iova_region_larb_msk
.../bindings/iommu/mediatek,iommu.yaml | 12 +-
drivers/iommu/mtk_iommu.c | 151 ++++--
.../memory/mediatek,mt8188-memory-port.h | 489 ++++++++++++++++++
include/soc/mediatek/smi.h | 1 +
4 files changed, 621 insertions(+), 32 deletions(-)
create mode 100644 include/dt-bindings/memory/mediatek,mt8188-memory-port.h
--
2.18.0
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