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Message-ID: <CAGXv+5HpWTTqrFKhkUDoZWa4h1wm=OuDHgFyMQsL-C4xKVfqOg@mail.gmail.com>
Date: Thu, 16 Feb 2023 15:54:23 +0800
From: Chen-Yu Tsai <wenst@...omium.org>
To: AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>
Cc: mturquette@...libre.com, sboyd@...nel.org, matthias.bgg@...il.com,
johnson.wang@...iatek.com, miles.chen@...iatek.com,
chun-jie.chen@...iatek.com, daniel@...rotopia.org,
fparent@...libre.com, msp@...libre.com, nfraprado@...labora.com,
rex-bc.chen@...iatek.com, zhaojh329@...il.com,
sam.shih@...iatek.com, edward-jw.yang@...iatek.com,
yangyingliang@...wei.com, granquet@...libre.com,
pablo.sun@...iatek.com, sean.wang@...iatek.com,
chen.zhong@...iatek.com, linux-kernel@...r.kernel.org,
linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org, kernel@...labora.com
Subject: Re: [PATCH v2 11/47] clk: mediatek: mt8365: Convert simple_gate to
mtk_gate clocks
On Tue, Feb 14, 2023 at 9:41 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com> wrote:
>
> On this SoC some clocks apparently don't have different offsets for
> set/clr/sta registers hence they can be set, cleared and status-read
> on one register: this means that it was possible to use simpler gate
> clocks instead of custom mtk_gate ones.
>
> In preparation for converting this clock driver to the common probe
> mechanism for MediaTek clocks, perform a conversion from simple_gate
> to mtk_gate clocks since the latter does provide implicit support
> for simple gate clocks as well.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
Reviewed-by: Chen-Yu Tsai <wenst@...omium.org>
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