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Message-ID: <CAGXv+5EepjwoVSZA=XFgwy_qiL3A2eZ7ZPBy-9Mb=D7OHYCjLQ@mail.gmail.com>
Date:   Thu, 16 Feb 2023 16:55:55 +0800
From:   Chen-Yu Tsai <wenst@...omium.org>
To:     AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@...labora.com>
Cc:     mturquette@...libre.com, sboyd@...nel.org, matthias.bgg@...il.com,
        johnson.wang@...iatek.com, miles.chen@...iatek.com,
        chun-jie.chen@...iatek.com, daniel@...rotopia.org,
        fparent@...libre.com, msp@...libre.com, nfraprado@...labora.com,
        rex-bc.chen@...iatek.com, zhaojh329@...il.com,
        sam.shih@...iatek.com, edward-jw.yang@...iatek.com,
        yangyingliang@...wei.com, granquet@...libre.com,
        pablo.sun@...iatek.com, sean.wang@...iatek.com,
        chen.zhong@...iatek.com, linux-kernel@...r.kernel.org,
        linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-mediatek@...ts.infradead.org, kernel@...labora.com
Subject: Re: [PATCH v2 20/47] clk: mediatek: mt8183: Convert all remaining
 clocks to common probe

On Tue, Feb 14, 2023 at 9:42 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com> wrote:
>
> Switch to mtk_clk_simple_{probe,remove}() for infracfg and topckgen
> clocks on MT8183 to allow full module build for clock drivers.
>
> Differently from other MediaTek clock drivers, it was necessary to
> change the name of the `clk13m` clock, as that is already declared
> in the SoC's devicetree as a "fixed-factor-clock" (with the same
> name) and redeclaring it here would obviously fail to register the
> entire clock controller; this clock wasn't dropped only to retain
> compatibility with older devicetrees
>
> As a note, the `clk13m` clock is not mentioned in any parent names
> array(s) as the correct one (csw_f26m_d2) is already used in place
> of that.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>

Reviewed-by: Chen-Yu Tsai <wenst@...omium.org>

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