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Message-ID: <20230217134107.13946-5-quic_devipriy@quicinc.com>
Date:   Fri, 17 Feb 2023 19:11:06 +0530
From:   Devi Priya <quic_devipriy@...cinc.com>
To:     <agross@...nel.org>, <andersson@...nel.org>,
        <konrad.dybcio@...aro.org>, <mturquette@...libre.com>,
        <sboyd@...nel.org>, <robh+dt@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>, <jassisinghbrar@...il.com>,
        <catalin.marinas@....com>, <will@...nel.org>,
        <dmitry.baryshkov@...aro.org>, <arnd@...db.de>,
        <geert+renesas@...der.be>, <nfraprado@...labora.com>,
        <broonie@...nel.org>, <rafal@...ecki.pl>,
        <linux-arm-msm@...r.kernel.org>, <linux-clk@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>
CC:     <quic_srichara@...cinc.com>, <quic_gokulsri@...cinc.com>,
        <quic_sjaganat@...cinc.com>, <quic_kathirav@...cinc.com>,
        <quic_arajkuma@...cinc.com>, <quic_anusha@...cinc.com>
Subject: [PATCH V2 4/5] arm64: dts: qcom: ipq9574: Add support for APSS clock controller

Add the APCS & A73 PLL nodes to support CPU frequency scaling

Co-developed-by: Praveenkumar I <quic_ipkumar@...cinc.com>
Signed-off-by: Praveenkumar I <quic_ipkumar@...cinc.com>
Signed-off-by: Devi Priya <quic_devipriy@...cinc.com>
---
 Changes in V2:
	- No changes

 arch/arm64/boot/dts/qcom/ipq9574.dtsi | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 70d920400265..d20f3c7383f5 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -405,6 +405,24 @@
 			};
 		};
 
+		apcs_glb: mailbox@...1000 {
+			compatible = "qcom,ipq9574-apcs-apps-global",
+				     "qcom,ipq6018-apcs-apps-global";
+			reg = <0x0b111000 0x1000>;
+			#clock-cells = <1>;
+			clocks = <&a73pll>, <&xo_board_clk>;
+			clock-names = "pll", "xo";
+			#mbox-cells = <1>;
+		};
+
+		a73pll: clock@...6000 {
+			compatible = "qcom,ipq9574-a73pll";
+			reg = <0x0b116000 0x40>;
+			#clock-cells = <0>;
+			clocks = <&xo_board_clk>;
+			clock-names = "xo";
+		};
+
 		timer@...0000 {
 			compatible = "arm,armv7-timer-mem";
 			reg = <0x0b120000 0x1000>;
-- 
2.17.1

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