linux-kernel - [PATCH] dt-bindings: drop Sagar Kadam from SiFive binding maintainership

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Date:   Fri, 17 Feb 2023 18:00:36 +0000
From:   Conor Dooley <conor@...nel.org>
To:     Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>
Cc:     conor@...nel.org, Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Marc Zyngier <maz@...nel.org>,
        Thierry Reding <thierry.reding@...il.com>,
        Uwe Kleine-König 
        <u.kleine-koenig@...gutronix.de>,
        Albert Ou <aou@...s.berkeley.edu>, linux-clk@...r.kernel.org,
        devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org,
        linux-kernel@...r.kernel.org, linux-pwm@...r.kernel.org,
        Conor Dooley <conor.dooley@...rochip.com>,
        Sagar Kadam <sagar.kadam@...nfive.com>,
        Sagar Kadam <sagar.kadam@...ive.com>
Subject: [PATCH] dt-bindings: drop Sagar Kadam from SiFive binding maintainership

From: Conor Dooley <conor.dooley@...rochip.com>

Sagar's email listed in maintainers is bouncing as his division was sold
off by the company. I attempted to contact him some days ago on what the
bounce email told me was his new contact information, but am yet to
receive a response.

Paul and Palmer are listed on each of the bindings, both of whom were
alive & well as of Wednesday so the bindings remain maintained.

CC: Sagar Kadam <sagar.kadam@...nfive.com>
CC: Sagar Kadam <sagar.kadam@...ive.com>
Link: https://lore.kernel.org/all/785425ca-4000-a7e4-16d6-4d68c91b158d@kernel.org/
Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
---
Palmer/Paul, as mentioned Wednesday, here you go!
---
 Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml | 1 -
 .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml       | 1 -
 Documentation/devicetree/bindings/pwm/pwm-sifive.yaml          | 1 -
 Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml    | 3 +--
 4 files changed, 1 insertion(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml b/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml
index c3be1b600007..c79e752283aa 100644
--- a/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml
+++ b/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml
@@ -8,7 +8,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: SiFive FU540 Power Reset Clock Interrupt Controller (PRCI)
 
 maintainers:
-  - Sagar Kadam <sagar.kadam@...ive.com>
   - Paul Walmsley  <paul.walmsley@...ive.com>
 
 description:
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 99e01f4d0a69..63bc89e13480 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -45,7 +45,6 @@ description:
   from S-mode. So add thead,c900-plic to distinguish them.
 
 maintainers:
-  - Sagar Kadam <sagar.kadam@...ive.com>
   - Paul Walmsley  <paul.walmsley@...ive.com>
   - Palmer Dabbelt <palmer@...belt.com>
 
diff --git a/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml b/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml
index 605c1766dba8..bae993128981 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml
+++ b/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml
@@ -8,7 +8,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: SiFive PWM controller
 
 maintainers:
-  - Sagar Kadam <sagar.kadam@...ive.com>
   - Paul Walmsley <paul.walmsley@...ive.com>
 
 description:
diff --git a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
index bf3f07421f7e..0551a0d1b3df 100644
--- a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
+++ b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
@@ -8,8 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: SiFive Composable Cache Controller
 
 maintainers:
-  - Sagar Kadam <sagar.kadam@...ive.com>
-  - Paul Walmsley  <paul.walmsley@...ive.com>
+  - Paul Walmsley <paul.walmsley@...ive.com>
 
 description:
   The SiFive Composable Cache Controller is used to provide access to fast copies
-- 
2.39.1