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Message-ID: <20230220174553.pgd53ao5d7wsfrx7@orel>
Date: Mon, 20 Feb 2023 18:45:53 +0100
From: Andrew Jones <ajones@...tanamicro.com>
To: Sunil V L <sunilvl@...tanamicro.com>
Cc: Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Paul Walmsley <paul.walmsley@...ive.com>,
"Rafael J . Wysocki" <rafael@...nel.org>,
Len Brown <lenb@...nel.org>,
Thomas Gleixner <tglx@...utronix.de>,
Marc Zyngier <maz@...nel.org>,
Jonathan Corbet <corbet@....net>,
linux-riscv@...ts.infradead.org, linux-acpi@...r.kernel.org,
linux-doc@...r.kernel.org, linux-kernel@...r.kernel.org,
Conor Dooley <conor.dooley@...rochip.com>,
Anup Patel <apatel@...tanamicro.com>,
Atish Patra <atishp@...osinc.com>,
"Rafael J . Wysocki" <rafael.j.wysocki@...el.com>
Subject: Re: [PATCH V2 12/21] RISC-V: cpufeature: Add ACPI support in
riscv_fill_hwcap()
On Thu, Feb 16, 2023 at 11:50:34PM +0530, Sunil V L wrote:
> On ACPI based systems, the information about the hart
> like ISA is provided by the RISC-V Hart Capabilities Table (RHCT).
> Enable filling up hwcap structure based on the information in RHCT.
>
> Signed-off-by: Sunil V L <sunilvl@...tanamicro.com>
> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@...el.com>
> ---
> arch/riscv/kernel/cpufeature.c | 41 ++++++++++++++++++++++++++++------
> 1 file changed, 34 insertions(+), 7 deletions(-)
>
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 93e45560af30..cb67d3fcbb56 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -6,12 +6,15 @@
> * Copyright (C) 2017 SiFive
> */
>
> +#include <linux/acpi.h>
> #include <linux/bitmap.h>
> #include <linux/ctype.h>
> #include <linux/libfdt.h>
> #include <linux/log2.h>
> #include <linux/module.h>
> #include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <asm/acpi.h>
> #include <asm/alternative.h>
> #include <asm/cacheflush.h>
> #include <asm/errata_list.h>
> @@ -93,7 +96,10 @@ void __init riscv_fill_hwcap(void)
> char print_str[NUM_ALPHA_EXTS + 1];
> int i, j, rc;
> unsigned long isa2hwcap[26] = {0};
> + struct acpi_table_header *rhct;
> + acpi_status status;
> unsigned long hartid;
> + unsigned int cpu;
>
> isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I;
> isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M;
> @@ -106,18 +112,36 @@ void __init riscv_fill_hwcap(void)
>
> bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX);
>
> - for_each_of_cpu_node(node) {
> + if (!acpi_disabled) {
> + status = acpi_get_table(ACPI_SIG_RHCT, 0, &rhct);
> + if (ACPI_FAILURE(status))
> + return;
> + }
> +
> + for_each_possible_cpu(cpu) {
> unsigned long this_hwcap = 0;
> DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX);
> const char *temp;
>
> - rc = riscv_of_processor_hartid(node, &hartid);
> - if (rc < 0)
> - continue;
> + if (acpi_disabled) {
> + node = of_cpu_device_node_get(cpu);
> + if (node) {
> + rc = riscv_of_processor_hartid(node, &hartid);
> + if (rc < 0)
> + continue;
This 'continue' and the one below need of_node_put() calls. Or,
restructure to ensure that the one of_node_put() call added below
is always called.
>
> - if (of_property_read_string(node, "riscv,isa", &isa)) {
> - pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");
> - continue;
> + if (of_property_read_string(node, "riscv,isa", &isa)) {
> + pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");
> + continue;
> + }
> + of_node_put(node);
> + }
> + } else {
> + rc = acpi_get_riscv_isa(rhct, get_acpi_id_for_cpu(cpu), &isa);
> + if (rc < 0) {
> + pr_warn("Unable to get ISA for the hart - %d\n", cpu);
> + continue;
> + }
> }
>
> temp = isa;
> @@ -248,6 +272,9 @@ void __init riscv_fill_hwcap(void)
> bitmap_and(riscv_isa, riscv_isa, this_isa, RISCV_ISA_EXT_MAX);
> }
>
> + if (!acpi_disabled)
> + acpi_put_table((struct acpi_table_header *)rhct);
> +
> /* We don't support systems with F but without D, so mask those out
> * here. */
> if ((elf_hwcap & COMPAT_HWCAP_ISA_F) && !(elf_hwcap & COMPAT_HWCAP_ISA_D)) {
> --
> 2.34.1
>
Thanks,
drew
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