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Message-ID: <20230220194726.meppdac4y7qdjsoj@orel>
Date: Mon, 20 Feb 2023 20:47:26 +0100
From: Andrew Jones <ajones@...tanamicro.com>
To: Sunil V L <sunilvl@...tanamicro.com>
Cc: Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Paul Walmsley <paul.walmsley@...ive.com>,
"Rafael J . Wysocki" <rafael@...nel.org>,
Len Brown <lenb@...nel.org>,
Thomas Gleixner <tglx@...utronix.de>,
Marc Zyngier <maz@...nel.org>,
Jonathan Corbet <corbet@....net>,
linux-riscv@...ts.infradead.org, linux-acpi@...r.kernel.org,
linux-doc@...r.kernel.org, linux-kernel@...r.kernel.org,
Conor Dooley <conor.dooley@...rochip.com>,
Anup Patel <apatel@...tanamicro.com>,
Atish Patra <atishp@...osinc.com>,
"Rafael J . Wysocki" <rafael.j.wysocki@...el.com>
Subject: Re: [PATCH V2 15/21] clocksource/timer-riscv: Refactor
riscv_timer_init_dt()
On Thu, Feb 16, 2023 at 11:50:37PM +0530, Sunil V L wrote:
> Refactor the timer init function such that few things can be
> shared by both DT and ACPI based platforms.
>
> Co-developed-by: Anup Patel <apatel@...tanamicro.com>
> Signed-off-by: Anup Patel <apatel@...tanamicro.com>
> Signed-off-by: Sunil V L <sunilvl@...tanamicro.com>
> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@...el.com>
> ---
> drivers/clocksource/timer-riscv.c | 82 +++++++++++++++----------------
> 1 file changed, 40 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
> index 1b4b36df5484..2ae8e300d303 100644
> --- a/drivers/clocksource/timer-riscv.c
> +++ b/drivers/clocksource/timer-riscv.c
> @@ -119,61 +119,28 @@ static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id)
> return IRQ_HANDLED;
> }
>
> -static int __init riscv_timer_init_dt(struct device_node *n)
> +static int __init riscv_timer_init_common(void)
> {
> - int cpuid, error;
> - unsigned long hartid;
> - struct device_node *child;
> - struct irq_domain *domain;
> + int error;
> + struct irq_domain *domain = NULL;
domain is always assigned below, so we don't need to set it NULL here.
> + struct fwnode_handle *intc_fwnode = riscv_get_intc_hwnode();
>
> - error = riscv_of_processor_hartid(n, &hartid);
> - if (error < 0) {
> - pr_warn("Not valid hartid for node [%pOF] error = [%lu]\n",
> - n, hartid);
> - return error;
> - }
> -
> - cpuid = riscv_hartid_to_cpuid(hartid);
> - if (cpuid < 0) {
> - pr_warn("Invalid cpuid for hartid [%lu]\n", hartid);
> - return cpuid;
> - }
> -
> - if (cpuid != smp_processor_id())
> - return 0;
> -
> - child = of_find_compatible_node(NULL, NULL, "riscv,timer");
> - if (child) {
> - riscv_timer_cannot_wake_cpu = of_property_read_bool(child,
> - "riscv,timer-cannot-wake-cpu");
> - of_node_put(child);
> - }
> -
> - domain = NULL;
> - child = of_get_compatible_child(n, "riscv,cpu-intc");
> - if (!child) {
> - pr_err("Failed to find INTC node [%pOF]\n", n);
> - return -ENODEV;
> - }
> - domain = irq_find_host(child);
> - of_node_put(child);
> + domain = irq_find_matching_fwnode(intc_fwnode, DOMAIN_BUS_ANY);
> if (!domain) {
> - pr_err("Failed to find IRQ domain for node [%pOF]\n", n);
> + pr_err("Failed to find irq_domain for INTC node [%pfwP]\n",
> + intc_fwnode);
> return -ENODEV;
> }
>
> riscv_clock_event_irq = irq_create_mapping(domain, RV_IRQ_TIMER);
> if (!riscv_clock_event_irq) {
> - pr_err("Failed to map timer interrupt for node [%pOF]\n", n);
> + pr_err("Failed to map timer interrupt for node [%pfwP]\n", intc_fwnode);
> return -ENODEV;
> }
>
> - pr_info("%s: Registering clocksource cpuid [%d] hartid [%lu]\n",
> - __func__, cpuid, hartid);
> error = clocksource_register_hz(&riscv_clocksource, riscv_timebase);
> if (error) {
> - pr_err("RISCV timer register failed [%d] for cpu = [%d]\n",
> - error, cpuid);
> + pr_err("RISCV timer registration failed [%d]\n", error);
> return error;
> }
>
> @@ -202,4 +169,35 @@ static int __init riscv_timer_init_dt(struct device_node *n)
> return error;
> }
>
> +static int __init riscv_timer_init_dt(struct device_node *n)
> +{
> + int cpuid, error;
> + unsigned long hartid;
> + struct device_node *child;
> +
> + error = riscv_of_processor_hartid(n, &hartid);
> + if (error < 0) {
> + pr_warn("Invalid hartid for node [%pOF] error = [%lu]\n",
> + n, hartid);
> + return error;
> + }
> +
> + cpuid = riscv_hartid_to_cpuid(hartid);
> + if (cpuid < 0) {
> + pr_warn("Invalid cpuid for hartid [%lu]\n", hartid);
> + return cpuid;
> + }
> +
> + if (cpuid != smp_processor_id())
> + return 0;
> +
> + child = of_find_compatible_node(NULL, NULL, "riscv,timer");
> + if (child) {
> + riscv_timer_cannot_wake_cpu = of_property_read_bool(child,
> + "riscv,timer-cannot-wake-cpu");
> + of_node_put(child);
> + }
need blank line here
> + return riscv_timer_init_common();
> +}
> +
> TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt);
> --
> 2.34.1
>
Otherwise,
Reviewed-by: Andrew Jones <ajones@...tanamicro.com>
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